Inventor

REOHR WILLIAM ROBERT

US53 patents

⚠️ This page may combine multiple inventors who share the name “REOHR WILLIAM ROBERT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

REOHR WILLIAM ROBERT

IBM

Segmented write line architecture for writing magnetic random access memories

Embedded thermal conductors for semiconductor chips

Dynamic memory architecture employing passive expiration of data

Dynamic memory architecture employing passive expiration of data

Cross-point memory architecture with improved selectivity

Interconnection network for connecting memory cells to sense amplifiers

Current sensing amplifier

Select line architecture for magnetic random access memories

Current sense amplifier

Memory array employing single three-terminal non-volatile storage elements

Non-volatile memory using ferroelectric gate field-effect transistors

Data-dependent field compensation for writing magnetic random access memories

Restore tracking system for DRAM

Embedded thermal conductors for semiconductor chips

Segmented word line architecture for cross point magnetic random access memory

Write circuit for a magnetic random access memory

Set associative cache memory system with reduced power consumption

Method for reducing power consumption in a set associative cache memory system

Frequency modification techniques that adjust an operating frequency to compensate for aging electronic components

Method and apparatus for transposing differential signals onto a set of binary signals to increase the information-carrying capacity of the original set of signals

Method and apparatus for transposing differential signals onto a set of binary signals to increase the information-carrying capacity of the original set of signals

Precharged bit decoder and sense amplifier with integrated latch usable in pipelined memories

Method and structure for asynchronous skip-ahead in synchronous pipelines

Memory design which facilitates incremental fetch and store requests off applied base address requests

Random access memory having an adaptable latency

Differential and hierarchical sensing for memory circuits

Latency-aware replacement system and method for cache memories

Magnetic random access memory using memory cells with rotated magnetic storage elements

Bidirectional data transfer path having increased bandwidth

Bidirectional data transfer path having increased bandwidth

Differential and hierarchical sensing for memory circuits

Enhanced sensing in a hierarchical memory architecture

Differential and hierarchical sensing for memory circuits

Enhanced sensing in a hierarchical memory architecture

Location-based placement algorithms for set associative cache memory

Magnetic random access memory using memory cells with rotated magnetic storage elements

Bidirectional data transfer path having increased bandwidth

Memory sensing method and apparatus

REOHR WILLIAM ROBERT

Superconducting cell array logic circuit system

Timing control in a quantum memory system

Superconducting distributed bidirectional current driver system

Enhanced data retention mode for dynamic memories

High voltage word line driver

JTL-based superconducting logic arrays and FPGAs

Timing control in a quantum memory system

Read and write enhancements for arrays of superconducting magnetic memory cells

MILLER DONALD L

Superconducting phase-controlled hysteretic magnetic Josephson junction JMRAM memory cell

NORTHROP GRUMMAN SYSTEMS CORP

JTL-based superconducting logic arrays and FPGAS

INFINEON TECHNOLOGIES CORP

Architecture for high-speed magnetic memories

KNEBEL DANIEL R

Frequency modification techniques that adjust an operating frequency to compensate for aging electronic components