Inventor

SILBERMAN JOEL ABRAHAM

US52 patents

⚠️ This page may combine multiple inventors who share the name “SILBERMAN JOEL ABRAHAM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SILBERMAN JOEL ABRAHAM

IBM

At-speed scan testing

32-bit and 64-bit dual mode rotator

Delayed matching signal generator and frequency multiplier using scaled delay networks

Multiple level cache memory with overlapped L1 and L2 memory access

Set associative cache memory system with reduced power consumption

Method for reducing power consumption in a set associative cache memory system

High-speed binary adder

Method and apparatus for accelerating instruction fetching for a processor

Set-associative cache memory having a built-in set prediction array

Processor including age tracking of issue queue instructions

Unified local clock buffer structures

Latching dynamic logic structure, and integrated circuit including same

Method and system for accessing a cache memory within a data processing system

Integrated logic and latch design with clock gating at static input signals

Processor cycle time independent pipeline cache and method for pipelining data from a cache

Memory design which facilitates incremental fetch and store requests off applied base address requests

Random access memory having an adaptable latency

Scan chain disable function for power saving

Low skew, power efficient local clock signal generation system

Processor and method of fetching an instruction that select one of a plurality of decoded fetch addresses generated in parallel to form a memory request

System and method for high-speed register renaming by counting

Content addressable memory accessed by the sum of two operands

Domino logic circuit having a clocked precharge

Method and apparatus for translating an effective address to a real address within a cache memory

Method and apparatus for loading an instruction buffer of a processor capable of out-of-order instruction issue

Memory circuit for reordering selected data in parallel with selection of the data from the memory circuit

Multi-port SRAM with reduced access requirements

Combined adder and decoder digital circuit

Apparatus for detecting multiple hits in a CAMRAM memory array

Method and apparatus for implementing microprocessor control logic using dynamic programmable logic arrays

Method and apparatus for reducing dynamic programmable logic array propagation delay

Method and apparatus for generating and logically combining less than (LT), greater than (GT), and equal to (EQ) condition code bits concurrently with the execution of an arithmetic or logical operation

High speed rotator with array method

Random carry-in for floating-point operations

Method and system for a speedup of a bit multiplier

Branch history table

Apparatus and method for generating memory access signals, and memory accessed using said signals

Method and system for accessing a cache memory within a data-processing system utilizing a pre-calculated comparison array

Multifunctional macro

Method for using read-only memory to generate controls for microprocessor

Method and apparatus for synthesizing levelized logic

Optimized burn-in for fixed time dynamic logic circuitry

Method and apparatus for generating true/complement signals

Self-resetting circuit timing correction

High speed incrementer with array method

Strobe circuit keeper arrangement providing reduced power consumption

Random carry-in for floating-point operations

Wire trimmed programmable logic array

Scan chain disable function for power saving

BISHOP JAMES WILSON

Processor including age tracking of issue queue instructions