Inventor

WATANABE YOHJI

JP41 patents

⚠️ This page may combine multiple inventors who share the name “WATANABE YOHJI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WATANABE YOHJI

TOSHIBA KK

Semiconductor memory device having bidirectional potential barrier switching element

Dynamic semiconductor memory device with high-speed serial-accessing column decoder

Delay circuit for semiconductor integrated circuit devices

Semiconductor memory device having redundancy system

Semiconductor memory device having redundancy system

Semiconductor integrated circuit device having fuses and fuse latch circuits

Irregular pitch layout for a semiconductor memory device

Exchangeable hierarchical data line structure

Dynamic semiconductor memory device having sense amplifier with compensated offset voltage

Dynamic semiconductor memory device having simultaneous operation of adjacent blocks

Semiconductor device with power supply mode-change controller for reliability testing

Dram with (1/2)VCC precharge and selectively operable limiting circuit

Semiconductor device with power supply voltage converter circuit

Semiconductor integrated circuit device

Semiconductor storage device formed to optimize test technique and redundancy technology

Semiconductor storage device formed to optimize test technique and redundancy technology

Semiconductor memory device of shared sense amplifier system

Semiconductor memory device

Semiconductor memory device

Dynamic random access memory having continuous data line equalization except at address translation during data reading

Semiconductor memory device with simultaneously activated elements and a redundancy scheme thereof

Semiconductor memory device with redundancy control circuits

FET reference voltage generator which is impervious to input voltage fluctuations

Semiconductor integrated circuit device having fuses and fuse latch circuits

Semiconductor memory device

Dynamic random access memory having continuous data line equalization except at address transition during data reading

Semiconductor memory device having bidirectional potential barrier switching element

Semiconductor storage device formed to optimize test technique and redundancy technology

Semiconductor integrated circuit device

Semiconductor memory device

Semiconductor memory device

Semiconductor device

Write amplifier for use in semiconductor memory device

IBM

Bit-line precharge current limiter for CMOS dynamic memories

Method and apparatus for redundancy word line replacement in a repairable semiconductor memory device

Random access memory having a flexible array redundancy scheme

Temperature and power supply adjusted address transition detector

Random access memory with a simple test arrangement

Random access memory and an improved bus arrangement therefor

TOKYO SHIBAURA ELECTRIC CO

Semiconductor memory device having redundancy system

SIEMENS AG KABUSHIKI KAISHA TO

Methods and apparatus for increasing data bandwidth in a dynamic memory device by generating a delayed address transition detection signal in response to a column address strobe signal