Inventor

PU HAN-PING

TW138 patents

⚠️ This page may combine multiple inventors who share the name “PU HAN-PING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PU HAN-PING

SILICONWARE PRECISION INDUSTRIES CO LTD

Module device of stacked semiconductor packages and method for fabricating the same

Chip packaging

Flip-chip semiconductor package with lead frame as chip carrier and fabrication method thereof

Chip carrier for semiconductor chip

Substrate structure of flip chip package

Stacked-die package structure

Semiconductor package

Stacked semiconductor structure and fabrication method thereof

Flip-chip package structure and method of fabricating the same

Flip chip semiconductor package

Flip-chip package structure and method of fabricating the same

Multi-chip semiconductor package

Stacked semiconductor packages

Semiconductor package without bonding wires and fabrication method thereof

Semiconductor package structure with reduced parasite capacitance and method of fabricating the same

Semiconductor package with heat dissipating structure

Semiconductor package and fabrication method thereof

Semiconductor package with heat sink attached to substrate

Ball grid array semiconductor package

Cavity-down tape ball grid array package assembly with grounded heat sink and method of fabricating the same

Method of fabricating a flip-chip ball-grid-array package with molded underfill

Method of bonding ball grid array package to circuit board without causing package collapse

Stack structure of semiconductor packages and method for fabricating the stack structure

Semiconductor package and fabrication method thereof

Method of underfilling a flip-chip semiconductor device

Multi-chip module package structure

Chip-on-chip based multi-chip module with molded underfill and method of fabricating the same

Semiconductor package with flash preventing mechanism and fabrication method thereof

Chip scale package structure with metal pads exposed from an encapsulant

Semiconductor package on which a semiconductor device can be stacked and fabrication method thereof

Semiconductor package having heat dissipating device with cooling fluid

Semiconductor package and fabrication method thereof

Semiconductor package with heat sink

Semiconductor package with heat sink

Method of fabricating BGA packages

TAIWAN SEMICONDUCTOR MFG CO LTD

Packaging of semiconductor device with antenna and heat spreader

Package, package structure with redistributing circuits and antenna elements and method of manufacturing the same

Package structure with reinforcement structures in a redistribution circuit structure and method of manufacturing the same

Semiconductor device and method

Semiconductor packages and methods of forming same

Bumps for chip scale packaging including under bump metal structures with different diameters

3D integrated circuit package processing with panel type lid

Method of manufacturing integrated fan-out package

PU HAN-PING

Wafer level package structure and fabrication methods

Method for fabricating chip scale package structure with metal pads exposed from an encapsulant

TAIWAN SEMICONDUCTOR MFG

Enhanced copper posts for wafer level chip scale packaging

Enhanced copper posts for wafer level chip scale packaging

SHIEH YUH CHERN

Reduced-stress bump-on-trace (BOT) structures

LIN CHUN-HUNG

Stress compensation layer for 3D packaging

HUANG CHIEN-PING

Method of fabricating stacked semiconductor structure