Inventor

DHABLANIA ATUL

US29 patents

⚠️ This page may combine multiple inventors who share the name “DHABLANIA ATUL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DHABLANIA ATUL

SONICWALL INC

Establishing simultaneous mesh node connections

Elastic security services and load balancing in a wireless mesh network

Instant secure wireless network setup

Elastic security services and load balancing in a wireless mesh network

Just in time memory analysis for malware detection

Instant secure wireless network setup

Network interface device having bypass capability

Instant secure wireless network setup

Securing transmission paths in a mesh network

Streamlined creation and expansion of a wireless mesh network

Analysis of historical network traffic to identify network vulnerabilities

Detecting profile-based wireless mesh node failover in communication networks

Visualization tool for real-time network risk assessment

Streamlined creation and expansion of a wireless mesh network

Elastic security services load balancing in a wireless mesh network

Analysis of historical network traffic to identify network vulnerabilities

Visualization tool for real-time network risk assessment

NAT SEMICONDUCTOR CORP

Formatting denormal numbers for processing in a pipelined floating point unit

Formatting denormal numbers for processing in a pipelined floating point unit

Integer to floating point conversion using one&#39;s complement with subsequent correction to eliminate two&#39;s complement in critical path

Converting negative floating point numbers to integer notation without two&#39;s complement hardware

Converting negative floating point numbers to integer notation without two&#39;s complement hardware

Leading bit prediction with in-parallel correction

Rounding denormalized numbers in a pipelined floating point unit without pipeline stalls

Leading bit prediction with in-parallel correction

FUJITSU LTD

Generation of sign extended shifted numerical values

Error detection in dynamic logic circuits

VIA CYRIX INC

Reloadable floating point unit

NAT SEMICONDCUTOR CORP

Rounding denormalized numbers in a pipelined floating point unit without pipeline stalls

Integer to floating point conversion using one's complement with subsequent correction to eliminate two's complement in critical path

Converting negative floating point numbers to integer notation without two's complement hardware

Converting negative floating point numbers to integer notation without two's complement hardware