Inventor
GRABOWSKI WAYNE B
US16 patents
⚠️ This page may combine multiple inventors who share the name “GRABOWSKI WAYNE B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ADVANCED ANALOGIC TECH INC
5 patentsUS6291298B1Sep 18, 2001
Process of manufacturing Trench gate semiconductor device having gate oxide layer with multiple thicknesses
ADVANCED ANALOGIC TECH INC212 citations99
US7238568B2Jul 3, 2007
Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same
ADVANCED ANALOGIC TECH INC12 citations92
US6900100B2May 31, 2005
Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same
ADVANCED ANALOGIC TECH INC29 citations92
US7282412B2Oct 16, 2007
Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same
ADVANCED ANALOGIC TECH INC5 citations74
US7276411B2Oct 2, 2007
Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same
ADVANCED ANALOGIC TECH INC5 citations74
POWER INTEGRATIONS INC
5 patentsUS5411901AMay 2, 1995
Method of making high voltage transistor
POWER INTEGRATIONS INC57 citations96
US5323044AJun 21, 1994
Bi-directional MOSFET switch
POWER INTEGRATIONS INC67 citations96
US5274259ADec 28, 1993
High voltage transistor
POWER INTEGRATIONS INC54 citations96
US9768274B2Sep 19, 2017
Laterally-graded doping of materials
POWER INTEGRATIONS INC2 citations72
US9472630B2Oct 18, 2016
Deposit/etch for tapered oxide
POWER INTEGRATIONS INC1 citations52
SILICONIX INC
4 patentsUS6204533B1Mar 20, 2001
Vertical trench-gated power MOSFET having stripe geometry and high cell density
SILICONIX INC86 citations98
US6140678AOct 31, 2000
Trench-gated power MOSFET with protective diode
SILICONIX INC92 citations98
US6078090AJun 20, 2000
Trench-gated Schottky diode with integral clamping diode
SILICONIX INC265 citations96
US6277695B1Aug 21, 2001
Method of forming vertical planar DMOSFET with self-aligned contact
SILICONIX INC52 citations91