Inventor

ARIMILLI LAKSHMINARAYANA BABA

US58 patents

⚠️ This page may combine multiple inventors who share the name “ARIMILLI LAKSHMINARAYANA BABA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ARIMILLI LAKSHMINARAYANA BABA

IBM

Method of cache management to dynamically update information-type dependent cache policies

Optimized cache allocation algorithm for multiple speculative requests

Method and system for bypassing cache levels when casting out from an upper level cache

Integrated cache and directory structure for multi-level caches

Cache management mechanism to enable information-type dependent cache policies

Data processing system, cache, and method that select a castout victim in response to the latencies of memory copies of cached data

Multiprocessor system bus protocol for O state memory-consistent data

Cache coherency protocol employing a read operation including a programmable flag to indicate deallocation of an intervened cache line

Multiprocessor system bus with a data-less castout mechanism

Multi-state logic analyzer integral to a microprocessor

Dynamically configurable memory bus and scalability ports via hardware monitored bus utilizations

Cache coherency protocol permitting sharing of a locked data granule

High speed lock acquisition mechanism with time parameterized cache coherency states

Extended cache coherency protocol with a modified store instruction lock release indicator

Extended cache coherency protocol with a “lock released” state

Mechanism for high performance transfer of speculative request data between levels of cache hierarchy

Time based mechanism for cached speculative data deallocation

Data processing system, cache, and method that utilize a coherency state to indicate the latency of cached data

Method of cache management to store information in particular regions of the cache according to information-type

Method for just in-time delivery of instructions in a data processing system

Cache allocation policy based on speculative request history

Data processing system, cache, and method of cache management including an O state for memory-consistent cache lines

Method and system for maintaining allocation information on data castout from an upper level cache

Method and system for allocating lower level cache entries for data castout from an upper level cache

Extended cache state with prefetched stream ID information

Method of cache management for dynamically disabling O state memory-consistent data

High performance multiprocessor system with modified-unsolicited cache state

Data processing system with configurable memory bus and scalability ports

Extended cache coherency protocol with a persistent “lock acquired” state

High performance multiprocessor system with exclusive-deallocate cache state

High performance mechanism to support O state horizontal cache-to-cache transfers

Cache allocation mechanism for modified-unsolicited cache state that modifies victimization priority bits

Method and system for high speed access to a banked cache memory

Method for just-in-time delivery of load data by intervening caches

Method and apparatus for forwarding data in a hierarchial cache memory architecture

Set-associative cache memory having incremental access latencies among sets

Cache coherency protocol in which a load instruction hint bit is employed to indicate deallocation of a modified cache line supplied by intervention

Dynamic mechanism to upgrade o state memory-consistent cache lines

Protocol for transferring modified-unsolicited state during data intervention

Multiprocessor system bus transaction for transferring exclusive-deallocate cache state to lower lever cache

Pre-transmission data reordering for a serial interface

Layered speculative request unit with instruction optimized and storage hierarchy optimized partitions

Method for instruction extensions for a tightly coupled speculative request unit

Multiprocessor system bus protocol with command and snoop responses for modified-unsolicited cache state

Method and apparatus for a data-less write operation within a cache memory hierarchy for a data processing system

ARIMILLI LAKSHMINARAYANA BABA

Techniques for dynamically assigning jobs to processors in a cluster based on broadcast information

Processor system and methods of triggering a block move using a system bus write command initiated by user code

Techniques for cache injection in a processor system responsive to a specific instruction sequence

Techniques for dynamically assigning jobs to processors in a cluster based on processor workload

Techniques for cache injection in a processor system from a remote node