Inventor

FIELDS JR JAMES STEPHEN

US111 patents

Patents

50 patents

US6848003B1Jan 25, 2005

Multi-node data processing system and communication protocol that route write data utilizing a destination ID obtained from a combined response

IBM87 citations98

US6754782B2Jun 22, 2004

Decentralized global coherency management in a multi-node computer system

IBM71 citations98

US6591321B1Jul 8, 2003

Multiprocessor system bus protocol with group addresses, responses, and priorities

IBM89 citations98

US6470427B1Oct 22, 2002

Programmable agent and method for managing prefetch queues

IBM82 citations98

US6434669B1Aug 13, 2002

Method of cache management to dynamically update information-type dependent cache policies

IBM95 citations98

US6405289B1Jun 11, 2002

Multiprocessor system in which a cache serving as a highest point of coherency is indicated by a snoop response

IBM148 citations98

US6393528B1May 21, 2002

Optimized cache allocation algorithm for multiple speculative requests

IBM97 citations98

US6356980B1Mar 12, 2002

Method and system for bypassing cache levels when casting out from an upper level cache

IBM90 citations98

US7421598B2Sep 2, 2008

Dynamic power management via DIMM read operation limiter

IBM69 citations97

US7194645B2Mar 20, 2007

Method and apparatus for autonomic policy-based thermal management in a data processing system

IBM63 citations97

US6275907B1Aug 14, 2001

Reservation management in a non-uniform memory access (NUMA) data processing system

IBM97 citations97

US6704843B1Mar 9, 2004

Enhanced multiprocessor response bus protocol enabling intra-cache line reference exchange

IBM59 citations96

US6615322B2Sep 2, 2003

Two-stage request protocol for accessing remote memory data in a NUMA data processing system

IBM70 citations96

US6473833B1Oct 29, 2002

Integrated cache and directory structure for multi-level caches

IBM76 citations96

US6425058B1Jul 23, 2002

Cache management mechanism to enable information-type dependent cache policies

IBM50 citations96

US6408362B1Jun 18, 2002

Data processing system, cache, and method that select a castout victim in response to the latencies of memory copies of cached data

IBM76 citations96

US6405290B1Jun 11, 2002

Multiprocessor system bus protocol for O state memory-consistent data

IBM55 citations96

US6282615B1Aug 28, 2001

Multiprocessor system bus with a data-less castout mechanism

IBM69 citations96

US6230219B1May 8, 2001

High performance multichannel DMA controller for a PCI host bridge with a built-in cache

IBM44 citations96

US7584329B2Sep 1, 2009

Data processing system and method for efficient communication utilizing an Ig coherency state

IBM36 citations93

US6901485B2May 31, 2005

Memory directory management in a multi-node computer system

IBM46 citations93

US6763433B1Jul 13, 2004

High performance cache intervention mechanism for symmetric multiprocessor systems

IBM36 citations93

US6760817B2Jul 6, 2004

Method and system for prefetching utilizing memory initiated prefetch write operations

IBM52 citations93

US6760809B2Jul 6, 2004

Non-uniform memory access (NUMA) data processing system having remote memory cache incorporated within system memory

IBM23 citations93

US6721856B1Apr 13, 2004

Enhanced cache management mechanism via an intelligent system bus monitor

IBM33 citations93

US6711652B2Mar 23, 2004

Non-uniform memory access (NUMA) data processing system that provides precise notification of remote deallocation of modified data

IBM53 citations93

US6658538B2Dec 2, 2003

Non-uniform memory access (NUMA) data processing system having a page table including node-specific data storage and coherency control

IBM52 citations93

US6633959B2Oct 14, 2003

Non-uniform memory access (NUMA) data processing system that provides notification of remote deallocation of shared data

IBM50 citations93

US6629210B1Sep 30, 2003

Intelligent cache management mechanism via processor access sequence analysis

IBM42 citations93

US6601144B1Jul 29, 2003

Dynamic cache management in a symmetric multiprocessor system via snoop operation sequence analysis

IBM53 citations93

US6591307B1Jul 8, 2003

Multi-node data processing system and method of queue management in which a queued operation is speculatively cancelled in response to a partial combined response

IBM25 citations93

US6532521B1Mar 11, 2003

Mechanism for high performance transfer of speculative request data between levels of cache hierarchy

IBM46 citations93

US6510494B1Jan 21, 2003

Time based mechanism for cached speculative data deallocation

IBM24 citations93

US6442653B1Aug 27, 2002

Data processing system, cache, and method that utilize a coherency state to indicate the latency of cached data

IBM27 citations93

US6434668B1Aug 13, 2002

Method of cache management to store information in particular regions of the cache according to information-type

IBM52 citations93

US6421762B1Jul 16, 2002

Cache allocation policy based on speculative request history

IBM19 citations93

US6397303B1May 28, 2002

Data processing system, cache, and method of cache management including an O state for memory-consistent cache lines

IBM38 citations93

US6385695B1May 7, 2002

Method and system for maintaining allocation information on data castout from an upper level cache

IBM41 citations93

US6370618B1Apr 9, 2002

Method and system for allocating lower level cache entries for data castout from an upper level cache

IBM30 citations93

US6360299B1Mar 19, 2002

Extended cache state with prefetched stream ID information

IBM30 citations93

US6345341B1Feb 5, 2002

Method of cache management for dynamically disabling O state memory-consistent data

IBM41 citations93

US6049841AApr 11, 2000

Data processing system and method for efficient storage of metadata in a system memory

IBM33 citations92

US7305522B2Dec 4, 2007

Victim cache using direct intervention

IBM40 citations92

US7116142B2Oct 3, 2006

Apparatus and method for accurately tuning the speed of an integrated circuit

IBM22 citations92

US7007210B2Feb 28, 2006

Method and system for handling multiple bit errors to enhance system reliability

IBM38 citations92

US7454577B2Nov 18, 2008

Data processing system and method for efficient communication utilizing an Tn and Ten coherency states

IBM14 citations84

US7308537B2Dec 11, 2007

Half-good mode for large L2 cache array topology with different latency domains

IBM11 citations84

Showing the top 50 of 111 patents by PatentIndex Score.

FIELDS JR JAMES STEPHEN

Patents

Multi-node data processing system and communication protocol that route write data utilizing a destination ID obtained from a combined response

Decentralized global coherency management in a multi-node computer system

Multiprocessor system bus protocol with group addresses, responses, and priorities

Programmable agent and method for managing prefetch queues

Method of cache management to dynamically update information-type dependent cache policies

Multiprocessor system in which a cache serving as a highest point of coherency is indicated by a snoop response

Optimized cache allocation algorithm for multiple speculative requests

Method and system for bypassing cache levels when casting out from an upper level cache

Dynamic power management via DIMM read operation limiter

Method and apparatus for autonomic policy-based thermal management in a data processing system

Reservation management in a non-uniform memory access (NUMA) data processing system

Enhanced multiprocessor response bus protocol enabling intra-cache line reference exchange

Two-stage request protocol for accessing remote memory data in a NUMA data processing system

Integrated cache and directory structure for multi-level caches

Cache management mechanism to enable information-type dependent cache policies

Data processing system, cache, and method that select a castout victim in response to the latencies of memory copies of cached data

Multiprocessor system bus protocol for O state memory-consistent data

Multiprocessor system bus with a data-less castout mechanism

High performance multichannel DMA controller for a PCI host bridge with a built-in cache

Data processing system and method for efficient communication utilizing an Ig coherency state

Memory directory management in a multi-node computer system

High performance cache intervention mechanism for symmetric multiprocessor systems

Method and system for prefetching utilizing memory initiated prefetch write operations

Non-uniform memory access (NUMA) data processing system having remote memory cache incorporated within system memory

Enhanced cache management mechanism via an intelligent system bus monitor

Non-uniform memory access (NUMA) data processing system that provides precise notification of remote deallocation of modified data

Non-uniform memory access (NUMA) data processing system having a page table including node-specific data storage and coherency control

Non-uniform memory access (NUMA) data processing system that provides notification of remote deallocation of shared data

Intelligent cache management mechanism via processor access sequence analysis

Dynamic cache management in a symmetric multiprocessor system via snoop operation sequence analysis

Multi-node data processing system and method of queue management in which a queued operation is speculatively cancelled in response to a partial combined response

Mechanism for high performance transfer of speculative request data between levels of cache hierarchy

Time based mechanism for cached speculative data deallocation

Data processing system, cache, and method that utilize a coherency state to indicate the latency of cached data

Method of cache management to store information in particular regions of the cache according to information-type

Cache allocation policy based on speculative request history

Data processing system, cache, and method of cache management including an O state for memory-consistent cache lines

Method and system for maintaining allocation information on data castout from an upper level cache

Method and system for allocating lower level cache entries for data castout from an upper level cache

Extended cache state with prefetched stream ID information

Method of cache management for dynamically disabling O state memory-consistent data

Method and apparatus of selecting data transmission channels

DMA cache control logic

Victim cache using direct intervention

Data processing system and method for efficient storage of metadata in a system memory

Victim cache using direct intervention

Apparatus and method for accurately tuning the speed of an integrated circuit

Method and system for handling multiple bit errors to enhance system reliability

Data processing system and method for efficient communication utilizing an Tn and Ten coherency states

Half-good mode for large L2 cache array topology with different latency domains