Inventor

SHIRLEY BRIAN M

US56 patents

⚠️ This page may combine multiple inventors who share the name “SHIRLEY BRIAN M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHIRLEY BRIAN M

MICRON TECHNOLOGY INC

Method and apparatus for simultaneous memory subarray testing

Method of storing a temperature threshold in an integrated circuit, method of modifying operation of dynamic random access memory in response to temperature, programmable temperature sensing circuit and memory integrated circuit

Integrated circuit power supply having piecewise linearity

Multi-bank memory

Low power auto-refresh circuit and method for dynamic random access memories

Method and system for using dynamic random access memory as cache memory

Method and system for using dynamic random access memory as cache memory

Low power auto-refresh circuit and method for dynamic random access memories

Asynchronous interface circuit and method for a pseudo-static memory device

Method of making a single-deposition-layer-metal dynamic random access memory

Method and system for hiding refreshes in a dynamic random access memory

Method and apparatus for repairing defective columns of memory cells

Timing fuse option for row repair

Memory device with single-ended sensing and low voltage pre-charge

Integrated chip multiplayer decoupling capacitors

Twisted global column decoder

Method and apparatus for simultaneous memory subarray testing

Circuit and method for a memory device with P-channel isolation gates

DRAM architecture with combined sense amplifier pitch

Integrated chip multilayer decoupling capacitors

Method and apparatus for quickly restoring digit I/O lines

Memory device tracking circuit

Method of storing a temperature threshold in an integrated circuit, method of modifying operation of dynamic random access memory in response to temperature, programmable temperature sensing circuit and memory integrated circuit

Memory device with regulated power supply control

Multi-bank memory

Method and apparatus for repairing defective columns of memory cells

Method and apparatus for quickly restoring digit I/O lines

Single deposition layer metal dynamic random access memory

Memory device tracking circuit

Method and system for using dynamic random access memory as cache memory

Asynchronous interface circuit and method for a pseudo-static memory device

Method and system for using dynamic random access memory as cache memory

Timing fuse method for delaying signals in a memory device

Single deposition layer metal dynamic random access memory

Circuit for providing isolation of integrated circuit active areas

Memory device with regulated power supply control

Twisted global column decoder

Circuit and method for a memory device with p-channel isolation gates

Integrated chip multilayer decoupling capcitors

Circuit and method for a memory device with p-channel isolation gates

Memory device tracking circuit

Memory device with regulated power supply control

Circuit for providing isolation of integrated circuit active areas

Method and apparatus for quickly restoring digit I/O lines

Multi-bank memory

Antifuse option for row repair

Twisted global column decoder

Circuit for providing isolation of integrated circuit active areas

ROUND ROCK RES LLC

Method and system for using dynamic random access memory as cache memory