Inventor
CHOU CHIEN-KANG
TW62 patents
⚠️ This page may combine multiple inventors who share the name “CHOU CHIEN-KANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
MEGICA CORP
33 patentsUS7969006B2Jun 28, 2011
Integrated circuit chips with fine-line metal and over-passivation metal
MEGICA CORP96 citations99
US8021918B2Sep 20, 2011
Integrated circuit chips with fine-line metal and over-passivation metal
MEGICA CORP45 citations98
US7372161B2May 13, 2008
Post passivation interconnection schemes on top of the IC chips
MEGICA CORP58 citations98
US7271489B2Sep 18, 2007
Post passivation interconnection schemes on top of the IC chips
MEGICA CORP69 citations98
US7470997B2Dec 30, 2008
Wirebond pad for semiconductor chip or wafer
MEGICA CORP66 citations97
US7208834B2Apr 24, 2007
Bonding structure with pillar and cap
MEGICA CORP59 citations97
US8004092B2Aug 23, 2011
Semiconductor chip with post-passivation scheme formed over passivation layer
MEGICA CORP42 citations96
US7423346B2Sep 9, 2008
Post passivation interconnection process and structures
MEGICA CORP48 citations96
US7397121B2Jul 8, 2008
Semiconductor chip with post-passivation scheme formed over passivation layer
MEGICA CORP49 citations96
US8004083B2Aug 23, 2011
Integrated circuit chips with fine-line metal and over-passivation metal
MEGICA CORP19 citations93
US7989954B2Aug 2, 2011
Integrated circuit chips with fine-line metal and over-passivation metal
MEGICA CORP21 citations93
US7960269B2Jun 14, 2011
Method for forming a double embossing structure
MEGICA CORP21 citations93
US7473999B2Jan 6, 2009
Semiconductor chip and process for forming the same
MEGICA CORP40 citations93
US7452803B2Nov 18, 2008
Method for fabricating chip structure
MEGICA CORP20 citations93
US7416971B2Aug 26, 2008
Top layers of metal for integrated circuits
MEGICA CORP36 citations93
US7381642B2Jun 3, 2008
Top layers of metal for integrated circuits
MEGICA CORP29 citations93
US7355282B2Apr 8, 2008
Post passivation interconnection process and structures
MEGICA CORP31 citations93
US8362588B2Jan 29, 2013
Semiconductor chip with coil element over passivation layer
MEGICA CORP14 citations92
US7960270B2Jun 14, 2011
Method for fabricating circuit component
MEGICA CORP14 citations92
US7582556B2Sep 1, 2009
Circuitry component and method for forming the same
MEGICA CORP40 citations92
US7547969B2Jun 16, 2009
Semiconductor chip with passivation layer comprising metal interconnect and contact pads
MEGICA CORP22 citations92
US7470927B2Dec 30, 2008
Semiconductor chip with coil element over passivation layer
MEGICA CORP30 citations92
US7468545B2Dec 23, 2008
Post passivation structure for a semiconductor device and packaging process for same
MEGICA CORP40 citations92
US7855461B2Dec 21, 2010
Chip structure with bumps and testing pads
MEGICA CORP19 citations91
US7394161B2Jul 1, 2008
Chip structure with pads having bumps or wirebonded wires formed thereover or used to be tested thereto
MEGICA CORP24 citations91
US8618580B2Dec 31, 2013
Integrated circuit chips with fine-line metal and over-passivation metal
MEGICA CORP8 citations84
US8373202B2Feb 12, 2013
Integrated circuit chips with fine-line metal and over-passivation metal
MEGICA CORP9 citations84
US7985653B2Jul 26, 2011
Semiconductor chip with coil element over passivation layer
MEGICA CORP8 citations84
US7964973B2Jun 21, 2011
Chip structure
MEGICA CORP8 citations84
US7482268B2Jan 27, 2009
Top layers of metal for integrated circuits
MEGICA CORP9 citations84
US7990037B2Aug 2, 2011
Carbon nanotube circuit component structure
MEGICA CORP6 citations74
US7521805B2Apr 21, 2009
Post passivation interconnection schemes on top of the IC chips
MEGICA CORP7 citations74
US7462558B2Dec 9, 2008
Method for fabricating a circuit component
MEGICA CORP7 citations74
LIN MOU-SHIUNG
10 patentsUS8884433B2Nov 11, 2014
Circuitry component and method for forming the same
LIN MOU-SHIUNG23 citations92
US8399989B2Mar 19, 2013
Metal pad or metal bump over pad exposed by passivation layer
LIN MOU-SHIUNG20 citations92
US8187965B2May 29, 2012
Wirebond pad for semiconductor chip or wafer
LIN MOU-SHIUNG20 citations92
US8558383B2Oct 15, 2013
Post passivation structure for a semiconductor device and packaging process for same
LIN MOU-SHIUNG16 citations84
US8552559B2Oct 8, 2013
Very thick metal interconnection scheme in IC chips
LIN MOU-SHIUNG9 citations84
US8319354B2Nov 27, 2012
Semiconductor chip with post-passivation scheme formed over passivation layer
LIN MOU-SHIUNG8 citations84
US8304907B2Nov 6, 2012
Top layers of metal for integrated circuits
LIN MOU-SHIUNG8 citations84
US8148822B2Apr 3, 2012
Bonding pad on IC substrate and method for making the same
LIN MOU-SHIUNG12 citations84
US8159074B2Apr 17, 2012
Chip structure
LIN MOU-SHIUNG3 citations63
US8120181B2Feb 21, 2012
Post passivation interconnection process and structures
LIN MOU-SHIUNG3 citations63
MEGIC CORP
2 patentsCHOU CHIEN-KANG
2 patentsCHOU CHIU-MING
2 patentsLEE JIN-YUAN
1 patentShowing the top 50 of 62 patents by PatentIndex Score.