Inventor

DENG XIAOWEI

US55 patents

⚠️ This page may combine multiple inventors who share the name “DENG XIAOWEI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DENG XIAOWEI

TEXAS INSTRUMENTS INC

SRAM cell with column select line

SRAM device and a method of powering-down the same

Bit line control for low power in standby

Dynamic threshold voltage 6T SRAM cell

Voltage keeping scheme for low-leakage memory devices

Low leakage SRAM scheme

Loadless 4T SRAM cell with PMOS drivers

CMOS latch and register circuitry using quantum mechanical tunneling structures

Memory cell layout structure with outer bitline

High performance SRAM device and method of powering-down the same

System and method for measuring a capacitance associated with an integrated circuit

Static random-access memory cell array with deep well regions

Structure and methods for measuring margins in an SRAM bit

Method for memory cell characterization using universal structure

Method and apparatus for determining capacitances for a device within an integrated circuit

Universal structure for memory cell characterization

Bit line control for low power in standby

Static logic design for CMOS

CMOS dynamic logic circuitry using quantum mechanical tunneling structures

SRAM with buffered-read bit cells and its testing

Method for constructing Shmoo plots for SRAMs

Logic array circuits using silicon-on-insulator logic

Array power supply-based screening of static random access memory cells for bias temperature instability

Leakage current reduction method

Array power supply-based screening of static random access memory cells for bias temperature instability

Array power supply-based screening of static random access memory cells for bias temperature instability

Array power supply-based screening of static random access memory cells for bias temperature instability

Array-based integrated circuit with reduced proximity effects

Method for testing transistors having an active region that is common with other transistors and a testing circuit for accomplishing the same

System for reducing row periphery power consumption in memory devices

System for reducing row periphery power consumption in memory devices

Silicon-on-insulator dynamic logic

DENG XIAOWEI

Efficient static random-access memory layout

Disturb-free static random access memory cell

Solid-state memory cell with improved read stability

Bit-by-bit write assist for solid-state memory

Memory cell with equalization write assist in solid-state memory

Margin testing of static random access memory cells

Array power supply-based screening of static random access memory cells for bias temperature instability

Reducing power in SRAM using supply voltage control

Characterization of bits in a functional memory

Method of screening static random access memories for unstable memory cells

Method and structure for SRAM cell trip voltage measurement

Structure and methods for measuring margins in an SRAM bit

Static random access memory cell with single-sided buffer and asymmetric construction

SRAM with buffered-read bit cells and its testing

Array-based integrated circuit with reduced proximity effects

Method and structure for SRAM Vmin/Vmax measurement

HOUSTON THEODORE W

Structure and method for screening SRAMS

PIOUS BEENA

Bitline leakage detection in memories