Inventor

RYU HYUK-JU

KR13 patents

⚠️ This page may combine multiple inventors who share the name “RYU HYUK-JU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SAMSUNG ELECTRONICS CO LTD

10 patents

US6855641B2Feb 15, 2005

CMOS transistor having different PMOS and NMOS gate electrode structures and method of fabrication thereof

SAMSUNG ELECTRONICS CO LTD31 citations92

US6548862B2Apr 15, 2003

Structure of semiconductor device and method for manufacturing the same

SAMSUNG ELECTRONICS CO LTD24 citations92

US7323420B2Jan 29, 2008

Method for manufacturing multi-thickness gate dielectric layer of semiconductor device

SAMSUNG ELECTRONICS CO LTD11 citations84

US7179750B2Feb 20, 2007

Method for manufacturing multi-thickness gate dielectric layer of semiconductor device

SAMSUNG ELECTRONICS CO LTD11 citations84

US7348636B2Mar 25, 2008

CMOS transistor having different PMOS and NMOS gate electrode structures and method of fabrication thereof

SAMSUNG ELECTRONICS CO LTD11 citations83

US7008835B2Mar 7, 2006

Method of manufacturing a semiconductor device having a gate structure with low parasitic capacitance

SAMSUNG ELECTRONICS CO LTD13 citations83

US6858907B2Feb 22, 2005

Method of fabricating semiconductor device having notched gate

SAMSUNG ELECTRONICS CO LTD14 citations83

US6764910B2Jul 20, 2004

Structure of semiconductor device and method for manufacturing the same

SAMSUNG ELECTRONICS CO LTD6 citations73

US7332400B2Feb 19, 2008

Method of manufacturing a semiconductor device having a gate structure with low parasitic capacitance

SAMSUNG ELECTRONICS CO LTD2 citations62

US7285831B2Oct 23, 2007

CMOS device with improved performance and method of fabricating the same

SAMSUNG ELECTRONICS CO LTD6 citations62

INTEL CORP

3 patents

US11145732B2Oct 12, 2021

RYU HYUK-JU

SAMSUNG ELECTRONICS CO LTD

CMOS transistor having different PMOS and NMOS gate electrode structures and method of fabrication thereof

Structure of semiconductor device and method for manufacturing the same

Method for manufacturing multi-thickness gate dielectric layer of semiconductor device

Method for manufacturing multi-thickness gate dielectric layer of semiconductor device

CMOS transistor having different PMOS and NMOS gate electrode structures and method of fabrication thereof

Method of manufacturing a semiconductor device having a gate structure with low parasitic capacitance

Method of fabricating semiconductor device having notched gate

Structure of semiconductor device and method for manufacturing the same

Method of manufacturing a semiconductor device having a gate structure with low parasitic capacitance

CMOS device with improved performance and method of fabricating the same

INTEL CORP

Field-effect transistors with dual thickness gate dielectrics

Stroboscopic electron-beam signal image mapping

Transistor arrangements with stacked trench contacts and gate straps