Inventor

SOMASEKHAR DINESH

US120 patents

⚠️ This page may combine multiple inventors who share the name “SOMASEKHAR DINESH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SOMASEKHAR DINESH

INTEL CORP

Floating-body memory cell write

Floating-body DRAM using write word line for increased retention time

Noise suppression for open bit line DRAM architectures

Low-leakage MOS planar capacitors for use within DRAM storage cells

Purge-based floating body memory

Level shifter

OTP antifuse cell and cell array

SRAM array with dynamic voltage for reducing active leakage power

Method and apparatus to clamp SRAM supply voltage

Wide-range local bias generator for body bias grid

Differential current switch logic gate

Capacitor, method of increasing a capacitance area of same, and system containing same

Memory having bit line with resistor(s) between memory cells

Memory with dynamically adjustable supply

2-transistor floating-body dram

Method and apparatus to clamp SRAM supply voltage

Reducing power consumption in integrated circuits

Dual gate oxide one time programmable (OTP) antifuse cell

Systolic memory arrays

Apparatus and method for programming a memory array

1P1N 2T gain cell

Floating-body dynamic random access memory and method of fabrication in tri-gate technology

Stable memory cell read

Method and apparatus for leakage compensation with full Vcc pre-charge

Static random access memory with symmetric leakage-compensated bit line

Pipelined compressor circuit

Apparatus and method for a memory storage cell leakage cancellation scheme

Flip flop circuit

Noise suppression for open bit line DRAM architectures

Flip flop circuit

Floating point multiply accumulator

Hiding refresh of memory and refresh-hidden memory

Digital outphasing transmitter architecture

Memory circuit

Memory cell driver circuits

Two transistor gain cell, method, and system

Crosspoint memory array utilizing one time programmable antifuse cells

Gating for dual edge-triggered clocking

Apparatus and method for a one-phase write to a one-transistor memory cell array

Floating-body DRAM using write word line for increased retention time

Memory cell leakage reduction

Tri-rail domino circuit

Apparatus and method for fusion of compute and switching functions of exascale system into a single component by using configurable network-on-chip fabric with distributed dual mode input-output ports and programmable network interfaces

Scalable polylithic on-package integratable apparatus and method

WOO YOUNGTAG

Double sidewall image transfer process

GLOBALFOUNDRIES INC

Double sidewall image transfer process

WILKERSON CHRISTOPHER B

Method and apparatus for using cache memory in a system that supports a low power state

LU SHIH-LIEN L

Low overhead error correcting code protection for stored information

WANG YIH

6F2 DRAM cell

DOYLE BRIAN S

Capacitor, method of increasing a capacitance area of same, and system containing same