Inventor

O'BRIEN KEVIN P

US80 patents

⚠️ This page may combine multiple inventors who share the name “O'BRIEN KEVIN P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

O'BRIEN KEVIN P

INTEL CORP

Method of forming a selectively converted inter-layer dielectric using a porogen material

Forming a porous dielectric layer

Formation of air gaps in an interconnect structure using a thin permeable hard mask and resulting structures

Forming thin hard mask over air gap or porous dielectric

Densifying a relatively porous material

Sacrificial dielectric planarization layer

Method of forming an air gap intermetal layer dielectric (ILD) by utilizing a dielectric material to bridge underlying metal lines

Photosensitive dielectric layer

Post polish anneal of atomic layer deposition barrier layers

Capping of copper structures in hydrophobic ILD using aqueous electro-less bath

Removing sacrificial material by thermal decomposition

Three-dimensional stacked substrate arrangements

Microelectronic assemblies with inductors in direct bonding regions

Microelectronic assemblies with inductors in direct bonding regions

Sacrificial dielectric planarization layer

Method to modulate etch rate in SLAM

Perpendicular magnetic memory with symmetric fixed layers

Low stray field magnetic memory

Electrical contacts for magnetoresistive random access memory devices

PSTTM device with bottom electrode interface material

PSTTM device with multi-layered filter stack

Perpendicular spin transfer torque memory (pSTTM) devices with enhanced stability and method to form same

Texture breaking layer to decouple bottom electrode from PMTJ device

Ferroelectric field-effect transistor devices having a top gate and a bottom gate

Stacked 2D CMOS with inter metal layers

Perpendicular STTM multi-layer insert free layer

Perpendicular magnetic memory with reduced switching current

Unipolar current switching in perpendicular magnetic tunnel junction (pMTJ) devices through reduced bipolar coercivity

Perpendicular magnetic memory with filament conduction path

Sealing porous dielectric materials

Conformal electroless deposition of barrier layer materials

Method to modulate etch rate in SLAM

Method of fabricating a bismaleimide (BMI) ASA sacrifical material for an integrated circuit air gap dielectric

Thin film transistors having semiconductor structures integrated with 2D channel materials

TMD inverted nanowire integration

TMD inverted nanowire integration

Charge-transfer spacers for stacked nanoribbon 2D transistors

High stability free layer for perpendicular spin torque transfer memory

Approaches for strain engineering of perpendicular magnetic tunnel junctions (pMTJs) and the resulting structures

Interconnect capping process for integration of MRAM devices and the resulting structures

Random number generator

Amine-free deposition of metal-nitride films

Thin film transistors having strain-inducing structures integrated with 2D channel materials

Integrated circuit structures with graphene contacts

BRIEN KEVIN P O

Spirometer with zone graph

Ridable recreation device

ELSHERBINI ADEL A

Magnetic core inductor (MCI) structures for integrated voltage regulators

RAMANATHAN SHRIRAM

Three-dimensional stacked substrate arrangements

DOYLE BRIAN S

Memory cells with enhanced tunneling magnetoresistance ratio, memory devices and systems including the same

JEZEWSKI CHRISTOPHER J

Vertical meander inductor for small core voltage regulators