Inventor

BRASK JUSTIN K

US181 patents

⚠️ This page may combine multiple inventors who share the name “BRASK JUSTIN K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BRASK JUSTIN K

INTEL CORP

Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric material

Field effect transistor with narrow bandgap source and drain regions and method of fabrication

Multilayer metal gate electrode

Nonplanar transistors with metal gate electrodes

Block contact architectures for nanoscale channel transistors

Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate

Methods for patterning a semiconductor film

Multigate device with recessed strain regions

Dielectric interface for group III-V semiconductor device

Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby

Stacked multi-gate transistor design and method of fabrication

Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode

Method for making a semiconductor device with a high-k gate dielectric and a metal gate electrode

Nonplanar transistors with metal gate electrodes

Nonplanar transistors with metal gate electrodes

Method of forming a metal oxide dielectric

Block contact architectures for nanoscale channel transistors

Device with scavenging spacer layer

Method for making a semiconductor device with a metal gate electrode that is formed on an annealed high-k gate dielectric layer

Methods for integrating replacement metal gate structures

Replacement gate process for making a semiconductor device that includes a metal gate electrode

Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode

CMOS device with metal and silicide gate electrodes and a method for making it

Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode

Semiconductor device with a high-k gate dielectric and a metal gate electrode

Method for making a semiconductor device having a high-k gate dielectric and a titanium carbide gate electrode

Epitaxially deposited source/drain

Controlled faceting of source/drain regions

Integrating n-type and p-type metal gate transistors

Method for making a semiconductor device having a high-k gate dielectric

Method for making a semiconductor device having a high-k gate dielectric

Field effect transistor with narrow bandgap source and drain regions and method of fabrication

Method for fabricating transistor with thinned channel

Nonplanar device with thinned lower body portion and method of fabrication

Method for making semiconductor device having a high-k gate dielectric layer and a metal gate electrode

Metal gate transistors with epitaxial source and drain regions

Forming high-k dielectric layers on smooth substrates

Integrating n-type and p-type metal gate transistors

Method for making a semiconductor device that includes a metal gate electrode

Planarizing a semiconductor structure to form replacement metal gates

Using different gate dielectrics with NMOS and PMOS transistors of a complementary metal oxide semiconductor integrated circuit

integrating n-type and P-type metal gate transistors

Integrating n-type and p-type metal gate transistors

Selective etching using sonication

Method for making a semiconductor device having a high-k gate dielectric

Method for making a semiconductor device having a high-k gate dielectric

Nonplanar transistors with metal gate electrodes

Forming a porous dielectric layer

Field effect transistor with narrow bandgap source and drain regions and method of fabrication

BRASK JUSTIN K

Semiconductor device structures and methods of forming semiconductor structures