Inventor
KOTECHA POOJA M
US8 patents
Patents
8 patentsUS7581201B2Aug 25, 2009
System and method for sign-off timing closure of a VLSI chip
IBM35 citations90
US7895556B2Feb 22, 2011
Method for optimizing an unrouted design to reduce the probability of timing problems due to coupling and long wire routes
IBM13 citations83
US7996812B2Aug 9, 2011
Method of minimizing early-mode violations causing minimum impact to a chip design
IBM16 citations82
US7987440B2Jul 26, 2011
Method and system for efficient validation of clock skews during hierarchical static timing analysis
IBM10 citations82
US6958545B2Oct 25, 2005
Method for reducing wiring congestion in a VLSI chip design
IBM8 citations72
US10417663B2Sep 17, 2019
Ephemeral geofence campaign system
IBM2 citations71
US10168857B2Jan 1, 2019
Virtual reality for cognitive messaging
IBM3 citations66
US10949884B2Mar 16, 2021
Ephemeral geofence campaign system
IBM0 citations61