Inventor
Odiz Eyal
US6 patents
Patents
6 patentsUS10372858B2Aug 6, 2019
Design-for-testability (DFT) insertion at register-transfer-level (RTL)
SYNOPSYS INC7 citations80
US9697314B1Jul 4, 2017
Identifying and using slices in an integrated circuit (IC) design
SYNOPSYS INC6 citations68
US9690890B1Jun 27, 2017
Creating and using a wide-bus data structure to represent a wide-bus in an integrated circuit (IC) design
SYNOPSYS INC4 citations68
US9652573B1May 16, 2017
Creating and using a wide-gate data structure to represent a wide-gate in an integrated circuit (IC) design
SYNOPSYS INC6 citations68
US10643012B1May 5, 2020
Concurrent formal verification of logic synthesis
SYNOPSYS INC3 citations60
US10354032B2Jul 16, 2019
Optimizing an integrated circuit (IC) design comprising at least one wide-gate or wide-bus
SYNOPSYS INC0 citations37