Inventor
OLSON JANET L
US5 patents
Patents
5 patentsUS10372858B2Aug 6, 2019
Design-for-testability (DFT) insertion at register-transfer-level (RTL)
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US9697314B1Jul 4, 2017
Identifying and using slices in an integrated circuit (IC) design
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US9690890B1Jun 27, 2017
Creating and using a wide-bus data structure to represent a wide-bus in an integrated circuit (IC) design
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US9652573B1May 16, 2017
Creating and using a wide-gate data structure to represent a wide-gate in an integrated circuit (IC) design
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US10354032B2Jul 16, 2019
Optimizing an integrated circuit (IC) design comprising at least one wide-gate or wide-bus
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