Inventor

MIU MING T

22 patents

⚠️ This page may combine multiple inventors who share the name “MIU MING T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MIU MING T

HONEYWELL INF SYSTEMS

Data processing system having synchronous bus wait/retry cycle

Program counter stacking method and apparatus for nested subroutines and interrupts

Data processing system having data multiplex control apparatus

Synchronization technique for data transfers over an asynchronous common bus network coupling data processing apparatus

Data processing system having centralized memory refresh

Microprogrammed system having hardware interrupt apparatus

Microprogrammed system having single microstep apparatus

Data processing system having centralized nonexistent memory address detection

Data processing system having centralized data alignment for I/O controllers

Data processing system having direct memory access bus cycle

Data processing interrupt apparatus having selective suppression control

Data processing system having multiple common buses

Data processing system having data multiplex control bus cycle

Data processing system self-test enabling technique

Data processing system having centralized bus priority resolution

Multiplication technique in a data processing system

Data processing system having data entry backspace character apparatus

Arithmetic logic unit with outputs indicating invalid computation results caused by invalid operands

HONEYWELL BULL

Virtual cache system using page level number generating CAM to access other memories for processing requests relating to a page

Least recently used replacement level generating apparatus

BULL HN INFORMATION SYST

Apparatus and method for simultaneous execution of a write instruction and a succeeding read instruction in a data processing system with a store through cache strategy

Apparatus and method for address translation of non-aligned double word virtual addresses