Inventor

KWAK JONGTAE

US64 patents

⚠️ This page may combine multiple inventors who share the name “KWAK JONGTAE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KWAK JONGTAE

MICRON TECHNOLOGY INC

System and method for an accuracy-enhanced DLL during a measure initialization mode

Circuit, system and method for controlling read latency

Clock generator having a delay locked loop and duty cycle correction circuit in a parallel configuration

Circuit, system and method for controlling read latency

Timing synchronization circuit with loop counter

Trimmable delay locked loop circuitry with improved initialization characteristics

Staggered DLL clocking on N-Detect QED to minimize clock command and delay path

Control of a variable delay line using line entry point to modify line power supply voltage

Seamless coarse and fine delay structure for high performance DLL

Error correction bit flipping scheme

Timing synchronization circuit with loop counter

Methods and apparatuses for controlling timing paths and latency based on a loop delay

Seamless coarse and fine delay structure for high performance DLL

System and method for an accuracy-enhanced DLL during a measure initialization mode

Trimmable delay locked loop circuitry with improved initialization characteristics

Apparatus and method for multi-phase clock generation

Apparatus and method for multi-phase clock generation

Delay line circuit

Delay line circuit

Apparatuses and methods for providing internal memory commands and control signals in semiconductor memories

Apparatuses and methods for implementing masked write commands

Delay line circuit

Error correction bit flipping scheme

Extended error detection for a memory device

Extended error detection for a memory device

Apparatuses and methods for error correction coding and data bus inversion for semiconductor memories

Error correction code scrub scheme

Circuit, system and method for controlling read latency

System and method for an accuracy-enhanced DLL during a measure initialization mode

Apparatuses and methods for providing internal memory commands and control signals in semiconductor memories

Apparatuses and methods for providing internal memory commands and control signals in semiconductor memories

Error correction code scrub scheme

Error correction bit flipping scheme

System and method for an accuracy-enhanced DLL during a measure initialization mode

Dynamic burst length output control in a memory

Control of a variable delay line using line entry point to modify line power supply voltage

Built-in system and method for testing integrated circuit timing parameters

Fast response time, low power phase detector circuits, devices and systems incorporating the same, and associated methods

Built-in system and method for testing integrated circuit timing parameters

Error control for memory device

Error control for memory device

Apparatuses and methods for error correction coding and data bus inversion for semiconductor memories

Divided clock control

KWAK JONGTAE

Timing synchronization circuit with loop counter

Seamless coarse and fine delay structure for high performance DLL

Circuit, system and method for controlling read latency

Apparatuses and methods for altering a forward path delay of a signal path

Seamless coarse and fine delay structure for high performance DLL

Multi-phase clock generation

MAZUMDER KALLOL

Apparatuses and methods for adjusting a minimum forward path delay of a signal path