Inventor

BARTLEY GERALD KEITH

US62 patents

⚠️ This page may combine multiple inventors who share the name “BARTLEY GERALD KEITH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BARTLEY GERALD KEITH

IBM

Multi-node architecture with daisy chain communication link configurable to operate in unidirectional and bidirectional modes

Daisy chainable memory chip

Method and stacked memory structure for implementing enhanced cooling of memory devices

Socket assembly with incorporated memory structure

Implementing tamper evident and resistant detection through modulation of capacitance

Multi-node architecture with daisy chain communication link configurable to operate in unidirectional and bidirectional modes

Memory chip for high capacity memory subsystem supporting replication of command data

Implementing decoupling capacitors with hot-spot thermal reduction on integrated circuit chips

Method and structure for connecting, stacking, and cooling chips on a flexible carrier

Memory controller and method for handling DMA operations during a page copy

Daisy chainable memory chip

Daisy chained memory system

Computer system having daisy chained self timed memory chips

Embedded probe-enabling socket with integral probe structures

Method and structure to control common mode impedance in fan-out regions

Method and structures for implementing impedance-controlled coupled noise suppressor for differential interface solder column array

Method and embedded bus bar structure for implementing power distribution

Memory chip for high capacity memory subsystem supporting multiple speed bus

Handling DMA operations during a page copy

Method and apparatus for implementing silicon wafer chip carrier passive devices

Implementing enhanced wiring capability for electronic laminate packages

Dual-mode memory chip for high capacity memory subsystem

High capacity memory subsystem architecture employing hierarchical tree configuration of memory modules

Handling DMA requests in a virtual memory environment

Implementing redundant memory access using multiple controllers on the same bank of memory

Implementing directory organization to selectively optimize performance or reliability

Dynamic reconfiguration of solid state memory device to replicate and time multiplex data over multiple data interfaces

Computer system having daisy chained memory chips

Memory controller for daisy chained memory chips

Memory chip having an apportionable data bus

Method for implementing component placement suspended within grid array packages for enhanced electrical performance

Memory system having self timed daisy chained memory chips

Self timed memory chip having an apportionable data bus

Dynamic reconfiguration of solid state memory device to replicate and time multiplex data over multiple data interfaces

Method and power control structure for managing plurality of voltage islands

Method and stiffener-embedded waveguide structure for implementing enhanced data transfer

Customized mesh plane, method and computer program product for creating customized mesh planes within electronic packages

Method and structure for implementing column attach coupled noise suppressor

Method and probe structure for implementing a single probe location for multiple signals

Method and apparatus for implementing automated electronic package transmission line characteristic impedance verification

Method for implementing enhanced wiring capability for electronic laminate packages

Method and apparatus for transferring data on a synchronous multi-drop

Self optimizing off chip driver

Apparatus and method for composite behavioral modeling for multiple-sourced integrated circuits

Flex strips for high frequency connectors

Apparatus, and computer program for implementing vertically coupled noise control through a mesh plane in an electronic package design

BARTLEY GERALD KEITH

Implementing selective rework for chip stacks and silicon carrier assemblies

Digital data architecture employing redundant links in a daisy chain of component modules

Enhanced architectural interconnect options enabled with flipped die on a multi-chip package

MAKI ANDREW BENSON

Method of enhancing on-chip inductance structure utilizing silicon through via technology