Inventor

BECKER DARRYL JOHN

US40 patents

⚠️ This page may combine multiple inventors who share the name “BECKER DARRYL JOHN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BECKER DARRYL JOHN

IBM

Daisy chainable memory chip

Socket assembly with incorporated memory structure

Method, structure, and computer program product for implementing high frequency return current paths within electronic packages

Method and structure for connecting, stacking, and cooling chips on a flexible carrier

Daisy chainable memory chip

Computer system having daisy chained self timed memory chips

Daisy chained memory system

Embedded probe-enabling socket with integral probe structures

Method and structure to control common mode impedance in fan-out regions

Method and structures for implementing impedance-controlled coupled noise suppressor for differential interface solder column array

Method, apparatus and computer program product for implementing enhanced high frequency return current paths utilizing decoupling capacitors in a package design

Method and apparatus for implementing silicon wafer chip carrier passive devices

Implementing enhanced wiring capability for electronic laminate packages

Implementing redundant memory access using multiple controllers on the same bank of memory

Computer system having daisy chained memory chips

Memory controller for daisy chained memory chips

Memory chip having an apportionable data bus

Method for implementing component placement suspended within grid array packages for enhanced electrical performance

Memory system having self timed daisy chained memory chips

Self timed memory chip having an apportionable data bus

Method and power control structure for managing plurality of voltage islands

Method and stiffener-embedded waveguide structure for implementing enhanced data transfer

Customized mesh plane, method and computer program product for creating customized mesh planes within electronic packages

Method and structure for implementing column attach coupled noise suppressor

Method for implementing enhanced wiring capability for electronic laminate packages

Apparatus, and computer program for implementing vertically coupled noise control through a mesh plane in an electronic package design

Method and apparatus for implementing redundant memory access using multiple controllers on the same bank of memory

Computer system having an apportionable data bus and daisy chained memory chips

Daisy chainable self timed memory chip

Carrier having daisy chained memory chips

Memory system having an apportionable data bus and daisy chained memory chips

Method for implementing vertically coupled noise control through a mesh plane in an electronic package design

Method and apparatus for implementing direct attenuation measurement through embedded structure excitation

Implementing at-speed Wafer Final Test (WFT) with complete chip coverage

Carrier having daisy chain of self timed memory chips

Memory controller for daisy chained self timed memory chips

BARTLEY GERALD KEITH

Implementing selective rework for chip stacks and silicon carrier assemblies

Digital data architecture employing redundant links in a daisy chain of component modules

Enhanced architectural interconnect options enabled with flipped die on a multi-chip package

MAKI ANDREW BENSON

Method of enhancing on-chip inductance structure utilizing silicon through via technology