Inventor

GERMANN PHILIP RAYMOND

US53 patents

⚠️ This page may combine multiple inventors who share the name “GERMANN PHILIP RAYMOND”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GERMANN PHILIP RAYMOND

IBM

Daisy chainable memory chip

Socket assembly with incorporated memory structure

Structure for hub for supporting high capacity memory subsystem

Memory chip for high capacity memory subsystem supporting replication of command data

Method and structure for connecting, stacking, and cooling chips on a flexible carrier

Daisy chainable memory chip

Daisy chained memory system

Computer system having daisy chained self timed memory chips

Embedded probe-enabling socket with integral probe structures

Method and structure to control common mode impedance in fan-out regions

Method and structures for implementing impedance-controlled coupled noise suppressor for differential interface solder column array

Method and embedded bus bar structure for implementing power distribution

Method and mechanical tamper-evident case fastener

Memory chip for high capacity memory subsystem supporting multiple speed bus

Method and apparatus for implementing silicon wafer chip carrier passive devices

Implementing enhanced wiring capability for electronic laminate packages

Method and structure for creating printed circuit boards with stepped thickness

Structure for memory chip for high capacity memory subsystem supporting multiple speed bus

Dual-mode memory chip for high capacity memory subsystem

High capacity memory subsystem architecture employing hierarchical tree configuration of memory modules

Implementing redundant memory access using multiple controllers on the same bank of memory

Computer system having daisy chained memory chips

Memory controller for daisy chained memory chips

Memory chip having an apportionable data bus

Method for implementing component placement suspended within grid array packages for enhanced electrical performance

Memory system having self timed daisy chained memory chips

Self timed memory chip having an apportionable data bus

Method and power control structure for managing plurality of voltage islands

Method and stiffener-embedded waveguide structure for implementing enhanced data transfer

Method and structure for implementing column attach coupled noise suppressor

Method and probe structure for implementing a single probe location for multiple signals

Method and apparatus for implementing automated electronic package transmission line characteristic impedance verification

Method for implementing enhanced wiring capability for electronic laminate packages

Self optimizing off chip driver

Structure for memory chip for high capacity memory subsystem supporting replication of command data

Apparatus, and computer program for implementing vertically coupled noise control through a mesh plane in an electronic package design

Hub for supporting high capacity memory subsystem

Method and apparatus for implementing redundant memory access using multiple controllers on the same bank of memory

Computer system having an apportionable data bus and daisy chained memory chips

Daisy chainable self timed memory chip

Carrier having daisy chained memory chips

Memory system having an apportionable data bus and daisy chained memory chips

Method for implementing vertically coupled noise control through a mesh plane in an electronic package design

Method and apparatus for implementing direct attenuation measurement through embedded structure excitation

Implementing at-speed Wafer Final Test (WFT) with complete chip coverage

Structure for dual-mode memory chip for high capacity memory subsystem

BARTLEY GERALD KEITH

Implementing selective rework for chip stacks and silicon carrier assemblies

Digital data architecture employing redundant links in a daisy chain of component modules

Enhanced architectural interconnect options enabled with flipped die on a multi-chip package

MAKI ANDREW BENSON

Method of enhancing on-chip inductance structure utilizing silicon through via technology