Inventor
MAKI ANDREW BENSON
US37 patents
⚠️ This page may combine multiple inventors who share the name “MAKI ANDREW BENSON”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
30 patentsUS7342816B2Mar 11, 2008
Daisy chainable memory chip
IBM27 citations92
US7074050B1Jul 11, 2006
Socket assembly with incorporated memory structure
IBM19 citations92
US7675164B2Mar 9, 2010
Method and structure for connecting, stacking, and cooling chips on a flexible carrier
IBM10 citations84
US7480201B2Jan 20, 2009
Daisy chainable memory chip
IBM8 citations84
US7345901B2Mar 18, 2008
Computer system having daisy chained self timed memory chips
IBM12 citations84
US7345900B2Mar 18, 2008
Daisy chained memory system
IBM13 citations84
US7202685B1Apr 10, 2007
Embedded probe-enabling socket with integral probe structures
IBM12 citations84
US7954081B2May 31, 2011
Implementing enhanced wiring capability for electronic laminate packages
IBM6 citations73
US7673093B2Mar 2, 2010
Computer system having daisy chained memory chips
IBM5 citations63
US7627711B2Dec 1, 2009
Memory controller for daisy chained memory chips
IBM6 citations63
US7620763B2Nov 17, 2009
Memory chip having an apportionable data bus
IBM4 citations63
US7553696B2Jun 30, 2009
Method for implementing component placement suspended within grid array packages for enhanced electrical performance
IBM4 citations63
US7545664B2Jun 9, 2009
Memory system having self timed daisy chained memory chips
IBM2 citations63
US7546410B2Jun 9, 2009
Self timed memory chip having an apportionable data bus
IBM5 citations63
US7402912B2Jul 22, 2008
Method and power control structure for managing plurality of voltage islands
IBM3 citations63
US7472360B2Dec 30, 2008
Method for implementing enhanced wiring capability for electronic laminate packages
IBM2 citations62
US7935546B2May 3, 2011
Method and apparatus for measurement and control of photomask to substrate alignment
IBM4 citations61
US7989337B2Aug 2, 2011
Implementing vertical airgap structures between chip metal layers
IBM4 citations60
US7979824B2Jul 12, 2011
Cost-benefit optimization for an airgapped integrated circuit
IBM2 citations60
US7875987B2Jan 25, 2011
Method and apparatus for measurement and control of photomask to substrate alignment
IBM3 citations60
US7532037B1May 12, 2009
Enhanced CML driver circuit for “quiet-driver” measurement enablement
IBM5 citations60
US7945883B2May 17, 2011
Apparatus, and computer program for implementing vertically coupled noise control through a mesh plane in an electronic package design
IBM0 citations52
US7844769B2Nov 30, 2010
Computer system having an apportionable data bus and daisy chained memory chips
IBM1 citations52
US7660942B2Feb 9, 2010
Daisy chainable self timed memory chip
IBM1 citations52
US7617350B2Nov 10, 2009
Carrier having daisy chained memory chips
IBM1 citations52
US7490186B2Feb 10, 2009
Memory system having an apportionable data bus and daisy chained memory chips
IBM1 citations52
US7472368B2Dec 30, 2008
Method for implementing vertically coupled noise control through a mesh plane in an electronic package design
IBM0 citations52
US7852103B2Dec 14, 2010
Implementing at-speed Wafer Final Test (WFT) with complete chip coverage
IBM1 citations51
US7660940B2Feb 9, 2010
Carrier having daisy chain of self timed memory chips
IBM0 citations42
US7577811B2Aug 18, 2009
Memory controller for daisy chained self timed memory chips
IBM0 citations42