Inventor
KULSHRESHTHA PAWAN
US8 patents
Patents
8 patentsUS8745561B1Jun 3, 2014
System and method for common path pessimism reduction in timing analysis to guide remedial transformations of a circuit design
CADENCE DESIGN SYSTEMS INC36 citations92
US10467365B1Nov 5, 2019
Systems and methods for calculating common clock path pessimism for hierarchical timing analysis in an electronic design
CADENCE DESIGN SYSTEMS INC21 citations91
US7647220B2Jan 12, 2010
Transistor-level timing analysis using embedded simulation
CADENCE DESIGN SYSTEMS INC10 citations83
US10169501B1Jan 1, 2019
Timing context generation with multi-instance blocks for hierarchical analysis
CADENCE DESIGN SYSTEMS INC7 citations82
US10037394B1Jul 31, 2018
Hierarchical timing analysis for multi-instance blocks
CADENCE DESIGN SYSTEMS INC8 citations82
US10460059B1Oct 29, 2019
System and method for generating reduced standard delay format files for gate level simulation
CADENCE DESIGN SYSTEMS INC8 citations78
US10133842B1Nov 20, 2018
Methods, systems, and articles of manufacture for multi-mode, multi-corner physical optimization of electronic designs
CADENCE DESIGN SYSTEMS INC4 citations68
US11188696B1Nov 30, 2021
Method, system, and product for deferred merge based method for graph based analysis pessimism reduction
CADENCE DESIGN SYSTEMS INC1 citations56