Inventor

MONY HARI

US97 patents

⚠️ This page may combine multiple inventors who share the name “MONY HARI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MONY HARI

IBM

Method and system for enhanced verification by closely coupling a structural overapproximation algorithm and a structural satisfiability solver

Exploiting suspected redundancy for enhanced design verification

Method for predicate-based compositional minimization in a verification environment

Method and system for parametric reduction of sequential designs

Method for verification using reachability overapproximation

Method for preserving constraints during sequential reparameterization

Sequential equivalence checking for asynchronous verification

Reversing the effects of sequential reparameterization on traces

Computer program product for extending incremental verification of circuit design to encompass verification restraints

Method for improved synthesis of binary decision diagrams with inverted edges and quantifiable as well as nonquantifiable variables

Method for improved synthesis of binary decision diagrams with inverted edges and quantifiable as well as nonquantifiable variables

Parametric reduction of sequential design

Method and system for performing utilization of traces for incremental refinement in coupling a structural overapproximation algorithm and a satisfiability solver

Using constraints in design verification

Method and system for performing minimization of input count during structural netlist overapproximation

Method for heuristic preservation of critical inputs during sequential reparameterization

Method and system for reversing the effects of sequential reparameterization on traces

Method for improved synthesis of binary decision diagrams with inverted edges and quantifiable as well as nonquantifiable variables

Method and system for reduction of XOR/XNOR subexpressions in structural design representations

Method and system for performing heuristic constraint simplification

System and method for engine-controlled case splitting within multiple-engine based verification framework

Method for retiming in the presence of verification constraints

Method and system for verifying the equivalence of digital circuits

Use of time step information in a design verification system

Incremental speculative merging

Design verification using sequential and combinational transformations

Method and system for reversing the effects of sequential reparameterization on traces

Using constraints in design verification

Method and system for performing heuristic constraint simplification

Method and system for performing heuristic constraint simplification

Extending incremental verification of circuit design to encompass verification restraints

System for verification using reachability overapproximation

Method for incremental design reduction via iterative overapproximation and re-encoding strategies

Method and system for enhanced verification through structural target decomposition

Method and system for enhanced verification through binary decision diagram-based target decomposition

Incremental, assertion-based design verification

Enhanced case-splitting based property checking

Adaptive bug-search depth for simple and deep counterexamples

BAUMGARTNER JASON R

Techniques for performing conditional sequential equivalence checking of an integrated circuit logic design

Enhanced analysis of array-based netlists via reparameterization

Efficient Redundancy Identification, Redundancy Removal, and Sequential Equivalence Checking within Designs Including Memory Arrays.

Constructing inductive counterexamples in a multi-algorithm verification framework

Method and system for optimal diameter bounding of designs with complex feed-forward components

Efficiently determining boolean satisfiability with lazy constraints

Method and system for optimal counterexample-guided proof-based abstraction

Method and system for scalable reduction in registers with SAT-based resubstitution

Techniques for analysis of logic designs with transient logic

Minimizing memory array representations for enhanced synthesis and verification

Optimal correlated array abstraction

CASE MICHAEL L

Logical circuit netlist reduction and model simplification using simulation results containing symbolic values