Inventor

PARUTHI VIRESH

US110 patents

⚠️ This page may combine multiple inventors who share the name “PARUTHI VIRESH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PARUTHI VIRESH

IBM

Method and system for enhanced verification by closely coupling a structural overapproximation algorithm and a structural satisfiability solver

Exploiting suspected redundancy for enhanced design verification

Method and system for equivalence-checking combinatorial circuits using interative binary-decision-diagram sweeping and structural satisfiability analysis

Method for predicate-based compositional minimization in a verification environment

Method and system for parametric reduction of sequential designs

Method for verification using reachability overapproximation

Method for preserving constraints during sequential reparameterization

Sequential equivalence checking for asynchronous verification

Framework for multiple-engine based verification tools for integrated circuits

Reversing the effects of sequential reparameterization on traces

Computer program product for extending incremental verification of circuit design to encompass verification restraints

Method for improved synthesis of binary decision diagrams with inverted edges and quantifiable as well as nonquantifiable variables

Method for improved synthesis of binary decision diagrams with inverted edges and quantifiable as well as nonquantifiable variables

Parametric reduction of sequential design

Method and system for performing utilization of traces for incremental refinement in coupling a structural overapproximation algorithm and a satisfiability solver

Using constraints in design verification

Method and system for performing minimization of input count during structural netlist overapproximation

Method for heuristic preservation of critical inputs during sequential reparameterization

Method and system for reversing the effects of sequential reparameterization on traces

Method for improved synthesis of binary decision diagrams with inverted edges and quantifiable as well as nonquantifiable variables

Method and system for reduction of XOR/XNOR subexpressions in structural design representations

Method and system for performing heuristic constraint simplification

Method and system for optimized handling of constraints during symbolic simulation

System and method for engine-controlled case splitting within multiple-engine based verification framework

Method for retiming in the presence of verification constraints

Method and system for building binary decision diagrams efficiently in a structural network representation of a digital circuit

Use of time step information in a design verification system

Verifying forwarding paths in pipelines

Verifying forwarding paths in pipelines

Enhancing formal design verification by reusing previous results

Incremental speculative merging

Design verification using sequential and combinational transformations

Method and system for performing functional verification of logic circuits

Method and system for reversing the effects of sequential reparameterization on traces

Using constraints in design verification

Method and system for performing heuristic constraint simplification

Method and system for performing heuristic constraint simplification

Extending incremental verification of circuit design to encompass verification restraints

System for verification using reachability overapproximation

Method for incremental design reduction via iterative overapproximation and re-encoding strategies

Method and system for enhanced verification through structural target decomposition

Method and system for enhanced verification through binary decision diagram-based target decomposition

Incremental, assertion-based design verification

Method, system and computer program product for verification of digital designs using case-splitting via constrained internal signals

Calculating an immediate parent assertion statement for program verification

Formal verification of arbiters

Formally deriving a minimal clock-gating scheme

Clock mapping in an integrated circuit design

Converting formal verification testbench drivers with nondeterministic inputs to simulation monitors

JANSSEN GRADUS GEERT

Circuit verification using computational algebraic geometry