Inventor

PONG FONG

US48 patents

⚠️ This page may combine multiple inventors who share the name “PONG FONG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PONG FONG

BROADCOM CORP

System-on-a-chip (SoC) device with integrated support for ethernet, TCP, iSCSI, RDMA, and network application acceleration

Method and system for on-chip configurable data ram for fast memory and pseudo associative caches

Method and system for hash table based routing via table and prefix aggregation

Area effective cache with pseudo associative memory

Global address space management

Memory management in a shared memory system

Memory management in a shared memory system

Shared memory architecture

Hardware memory locks

Method and system for supporting efficient and cache-friendly TCP session lookup operations based on canonicalization tags

Apparatus and methods for efficient insertion and removal of MPA markers and RDMA CRC digest

Network architecture with a light-weight TCP stack

Ring-based cache coherent bus

High bandwidth split bus

Global address space management

Method and system for hash table based routing via a prefix transformation

High bandwidth split bus

PONG FONG

Secure memory access controller

Shared memory architecture

Packet processing architecture

Adaptive cache for caching context and for adapting to collisions in a session lookup table

Hardware memory locks

Transmission using multiple physical interface

SoC device with integrated supports for Ethernet, TCP, iSCSI, RDMA and network application acceleration

Shared memory architecture

Apparatus and methods for efficient insertion and removal of MPA markers and RDMA CRC digest

SUN MICROSYSTEMS INC

Speculative cache line write backs to avoid hotspots

Apparatus and method for implementing a snoop bus protocol without snoop-in and snoop-out logic

Integrated processor/memory device with victim data cache

Integrated processor/memory device with victim data cache

Reducing bandwidth and areas needed for non-inclusive memory hierarchy by using dual tags

Processor/memory device with integrated CPU, main memory, and full width cache and associated method

Reducing cache misses by snarfing writebacks in non-inclusive memory systems

Method and apparatus for relaxing the FIFO ordering constraint for memory accesses in a multi-processor asynchronous cache system

HEWLETT PACKARD DEVELOPMENT CO

Multi-processor computer system with transactional memory

System and method for tracking and processing parallel coherent memory accesses

Cache-flushing engine for distributed shared memory multi-processor computer systems

Multi-processor computer system with lock driven cache-flushing system

System and method for recovering from memory failures in computer systems

Multi-processor computer system with cache-flushing system using memory recall

Caching method using cache tag and cache data stored in dynamic RAM embedded in logic chip

HEWLETT PACKARD CO

Transactional memory for distributed shared memory multi-processor computer systems

System and method for enhancing the reliability of a computer system by combining a cache sync-flush engine with a replicated memory module

Caching method using cache data stored in dynamic RAM embedded in logic chip and cache tag stored in static RAM external to logic chip

SYRUS ZIAI

Methods and systems for processing network data

Method and apparatus for calculating TCP and UDP checksums while preserving CPU resources

HEWLETT PACKARD COMPANY L P

Multi-processor computer system with cache-flushing system using memory recall

(unassigned)

Computer system and method for enhancing memory-to-memory copy transactions by utilizing multiple system control units