Inventor

LOH WAH KIT

US37 patents

⚠️ This page may combine multiple inventors who share the name “LOH WAH KIT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LOH WAH KIT

TEXAS INSTRUMENTS INC

On-chip temperature sensor and oscillator for reduced self-refresh current for dynamic random access memory

Method for reducing SRAM test time by applying power-up state knowledge

Memory regulator control method with flexibility for a wide change in supply voltage

Static random-access memory cell array with deep well regions

Structure and methods for measuring margins in an SRAM bit

Method for memory cell characterization using universal structure

SRAM static noise margin test structure suitable for on chip parametric measurements

Low power substrate bias circuit

ROM embedded mask release number for built-in self-test

Read-current and word line delay path tracking for sense amplifier enable timing

Method for determining and classifying SRAM bit fail modes suitable for production test implementation and real time feedback

SRAM with buffered-read bit cells and its testing

Method for constructing Shmoo plots for SRAMs

Array power supply-based screening of static random access memory cells for bias temperature instability

Array power supply-based screening of static random access memory cells for bias temperature instability

Array power supply-based screening of static random access memory cells for bias temperature instability

Array power supply-based screening of static random access memory cells for bias temperature instability

Array-based integrated circuit with reduced proximity effects

Functional screening of static random access memories using an array bias voltage

CMOS process to improve SRAM yield

DENG XIAOWEI

Margin testing of static random access memory cells

Array power supply-based screening of static random access memory cells for bias temperature instability

Method of screening static random access memories for unstable memory cells

Method and structure for SRAM cell trip voltage measurement

Structure and methods for measuring margins in an SRAM bit

Static random access memory cell with single-sided buffer and asymmetric construction

SRAM with buffered-read bit cells and its testing

Array-based integrated circuit with reduced proximity effects

Method and structure for SRAM Vmin/Vmax measurement

SESHADRI ANAND

Method of screening static random access memory cells for positive bias temperature instability

Low power retention random access memory with error correction on wake-up

YU SHAOFENG

Asymmetric static random access memory cell with dual stress liner

CMOS process to improve SRAM yield

LOH WAH KIT

SRAM power reduction through selective programming

Repairing soft failures in memory cells in SRAM arrays

PIOUS BEENA

Method of screening static random access memories for pass transistor defects

Bitline leakage detection in memories