Inventor

LEE TAK K

US60 patents

⚠️ This page may combine multiple inventors who share the name “LEE TAK K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEE TAK K

BROADCOM CORP

LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices

Overlapping sub-matrix based LDPC (low density parity check) decoder

LDPC (Low Density Parity Check) coding and interleaving implemented in MIMO communication systems

All digital reference frequency locking

Symbol mapping for binary coding

Turbo decoder employing ARP (almost regular permutation) interleave and arbitrary number of decoding processors

Combined LDPC (low density parity check) encoder and syndrome checker

Register exchange network for radix-4 SOVA (Soft-Output Viterbi Algorithm)

Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices

Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices

Construction of irregular LDPC (low density parity check) codes using RS (Reed-Solomon) codes or GRS (generalized Reed-Solomon) code

Sub-matrix-based implementation of LDPC (Low Density Parity Check) decoder

Multi-dimensional space Gray code maps for multi-dimensional phase modulation as applied to LDPC (Low Density Parity Check) coded modulation

System and method for interleaving data in a communications device

LDPC (low density parity check) code size adjustment by shortening and puncturing

Very short size LDPC coding for physical and/or control channel signaling

System and method for adjusting the phase of a frequency-locked clock

Multi-CSI (cyclic shifted identity) sub-matrix based LDPC (low density parity check) codes

LDPC (low density parity check) codes with corresponding parity check matrices selectively constructed with CSI (cyclic shifted identity) and null sub-matrices

General and algebraic-constructed contention-free memory mapping for parallel turbo decoding with algebraic interleave ARP (almost regular permutation) of all possible sizes

Address generation for contention-free memory mappings of turbo codes with ARP (almost regular permutation) interleaves

Partial-parallel implementation of LDPC (Low Density Parity Check) decoders

Implementation of LDPC (low density parity check) decoder by sweeping through sub-matrices

System and method for adjusting the phase of a frequency-locked clock

Symbol mapping for binary coding

Optimal period rate matching for turbo coding

Low density parity check (LDPC) coding in communication systems

SHEN BA-ZHONG

Quasi-cyclic LDPC (low density parity check) code construction

Single CRC polynomial for both turbo code block CRC and transport block CRC

LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices

LDPC (low density parity check) code size adjustment by shortening and puncturing

LDPC (low density parity check) coding and interleaving implemented in MIMO communication systems

Flexible rate matching

Turbo coding having combined turbo de-padding and rate matching de-padding

Reduced complexity ARP (almost regular permutation) interleaves providing flexible granularity and parallelism adaptable to any possible turbo code block size

LDPC (low density parity check) codes with corresponding parity check matrices selectively constructed with CSI (cyclic shifted identity) and null sub-matrices

Optimal period rate matching for turbo coding

Single CRC polynomial for both turbo code block CRC and transport block CRC

Flexible rate matching

Multi-CSI (Cyclic Shifted Identity) sub-matrix based LDPC (Low Density Parity Check) codes

Tail-biting turbo coding to accommodate any information and/or interleaver block size

Formulaic flexible collision-free memory accessing for parallel turbo decoding with quadratic polynomial permutation (QPP) interleave

Virtual limited buffer modification for rate matching

Turbo coding having combined turbo de-padding and rate matching de-padding

Formulaic flexible collision-free memory accessing for parallel turbo decoding with quadratic polynomial permutation (QPP) interleave

Virtual limited buffer modification for rate matching

LEE TAK K

Data puncturing ensuring orthogonality within communication systems

Fixed-spacing parity insertion for FEC (Forward Error Correction) codewords

TRAN HAU THIEN

Overlapping sub-matrix based LDPC (low density parity check) decoder

Overlapping sub-matrix based LDPC (low density parity check) decoder