Inventor
BRAYTON JAMES M
US6 patents
Patents
6 patentsUS5623628AApr 22, 1997
Computer system and method for maintaining memory consistency in a pipelined, non-blocking caching bus request queue
INTEL CORP296 citations98
US5682516AOct 28, 1997
Computer system that maintains system wide cache coherency during deferred communication transactions
INTEL CORP58 citations96
US5909699AJun 1, 1999
Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency
INTEL CORP19 citations92
US5797026AAug 18, 1998
Method and apparatus for self-snooping a bus during a boundary transaction
INTEL CORP41 citations92
US5572702ANov 5, 1996
Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency
INTEL CORP40 citations92
US5535345AJul 9, 1996
Method and apparatus for sequencing misaligned external bus transactions in which the order of completion of corresponding split transaction requests is guaranteed
INTEL CORP43 citations88