Inventor
LI YONGGANG
US54 patents
⚠️ This page may combine multiple inventors who share the name “LI YONGGANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
28 patentsUS7749900B2Jul 6, 2010
Method and core materials for semiconductor packaging
INTEL CORP26 citations92
US7485017B2Feb 3, 2009
Pin grid array package substrate including pins having anchoring elements
INTEL CORP20 citations92
US8928151B2Jan 6, 2015
Hybrid core through holes and vias
INTEL CORP7 citations84
US10306760B2May 28, 2019
Method of forming a substrate core structure using microvia laser drilling and conductive layer pre-patterning and substrate core structure formed according to the method
INTEL CORP6 citations83
US7407878B2Aug 5, 2008
Method of providing solder bumps on a substrate using localized heating
INTEL CORP7 citations74
US11081768B2Aug 3, 2021
Fabricating an RF filter on a semiconductor package using selective seeding
INTEL CORP2 citations73
US9716084B2Jul 25, 2017
Multichip integration with through silicon via (TSV) die embedded in package
INTEL CORP3 citations73
US9554472B2Jan 24, 2017
Panel with releasable core
INTEL CORP2 citations72
US12230430B2Feb 18, 2025
Substrate embedded magnetic core inductors and method of making
INTEL CORP0 citations62
US11605867B2Mar 14, 2023
Fabricating an RF filter on a semiconductor package using selective seeding
INTEL CORP0 citations62
US11404389B2Aug 2, 2022
In-situ component fabrication of a highly efficient, high inductance air core inductor integrated into substrate packages
INTEL CORP0 citations62
US11348718B2May 31, 2022
Substrate embedded magnetic core inductors and method of making
INTEL CORP0 citations62
US9397079B2Jul 19, 2016
Multichip integration with through silicon via (TSV) die embedded in package
INTEL CORP1 citations62
US7923059B2Apr 12, 2011
Method of enabling selective area plating on a substrate
INTEL CORP2 citations62
US12568831B2Mar 3, 2026
Patternable die attach materials and processes for patterning
INTEL CORP0 citations61
US12345932B2Jul 1, 2025
Die last and waveguide last architecture for silicon photonic packaging
INTEL CORP0 citations61
US11923312B2Mar 5, 2024
Patternable die attach materials and processes for patterning
INTEL CORP0 citations61
US12412868B2Sep 9, 2025
Microelectronic assemblies including interconnects with different solder materials
INTEL CORP0 citations60
US10910327B2Feb 2, 2021
Electronic device package with reduced thickness variation
INTEL CORP0 citations60
US10985080B2Apr 20, 2021
Electronic package that includes lamination layer
INTEL CORP0 citations59
US12354931B2Jul 8, 2025
Optimization for raster scanning
INTEL CORP0 citations58
US12327749B2Jun 10, 2025
Carrier chuck and methods of forming and using thereof
INTEL CORP0 citations52
US10672701B2Jun 2, 2020
Thin electronic package elements using laser spallation
INTEL CORP0 citations52
US9820390B2Nov 14, 2017
Process for forming a semiconductor device substrate
INTEL CORP0 citations52
US12027466B2Jul 2, 2024
Conductive route patterning for electronic substrates
INTEL CORP0 citations51
US12560771B2Feb 24, 2026
Die first fan-out architecture for electric and optical integration
INTEL CORP0 citations50
US11728265B2Aug 15, 2023
Selective deposition of embedded thin-film resistors for semiconductor packaging
INTEL CORP0 citations48
US10290557B2May 14, 2019
Selective metallization of an integrated circuit (IC) substrate
INTEL CORP0 citations46
LI YONGGANG
6 patentsUS8440916B2May 14, 2013
Method of forming a substrate core structure using microvia laser drilling and conductive layer pre-patterning and substrate core structure formed according to the method
LI YONGGANG17 citations91
US8318536B2Nov 27, 2012
Utilizing aperture with phase shift feature in forming microvias
LI YONGGANG6 citations73
US9648733B2May 9, 2017
Method of forming a substrate core structure using microvia laser drilling and conductive layer pre-patterning and substrate core structure formed according to the method
LI YONGGANG3 citations72
US7891091B2Feb 22, 2011
Method of enabling selective area plating on a substrate
LI YONGGANG3 citations62
US9442286B2Sep 13, 2016
Spaced configuration of acousto-optic deflectors for laser beam scanning of a semiconductor substrate
LI YONGGANG1 citations52
US8456016B2Jun 4, 2013
Method and core materials for semiconductor packaging
LI YONGGANG1 citations51
UNIV CENTRAL FLORIDA
3 patentsHEFEI VISIONOX TECH CO LTD
2 patentsRAORANE DIGVIJAY A
1 patentROY MIHIR K
1 patentBCHIR OMAR J
1 patentROY MIHIR
1 patentQUICK NATHANIEL R
1 patentSMR PATENTS SARL
1 patentGUZEK JOHN
1 patentSALAMA ISLAM
1 patentNANJING BREADY ELECTRONICS CO LTD
1 patentUNIV EAST CHINA SCIENCE & TECH
1 patentSHARKNINJA OPERATING LLC
1 patentShowing the top 50 of 54 patents by PatentIndex Score.