Inventor
PALLINTI JAYANTHI
US20 patents
⚠️ This page may combine multiple inventors who share the name “PALLINTI JAYANTHI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
LSI LOGIC CORP
16 patentsUS6391768B1May 21, 2002
Process for CMP removal of excess trench or via filler metal which inhibits formation of concave regions on oxide surface of integrated circuit structure
LSI LOGIC CORP28 citations92
US6060370AMay 9, 2000
Method for shallow trench isolations with chemical-mechanical polishing
LSI LOGIC CORP20 citations92
US6503828B1Jan 7, 2003
Process for selective polishing of metal-filled trenches of integrated circuit structures
LSI LOGIC CORP21 citations91
US6417093B1Jul 9, 2002
Process for planarization of metal-filled trenches of integrated circuit structures by forming a layer of planarizable material over the metal layer prior to planarizing
LSI LOGIC CORP52 citations91
US6607967B1Aug 19, 2003
Process for forming planarized isolation trench in integrated circuit structure on semiconductor substrate
LSI LOGIC CORP19 citations84
US6752916B1Jun 22, 2004
Electrochemical planarization end point detection
LSI LOGIC CORP10 citations73
US6424019B1Jul 23, 2002
Shallow trench isolation chemical-mechanical polishing process
LSI LOGIC CORP9 citations73
US7205673B1Apr 17, 2007
Reduce or eliminate IMC cracking in post wire bonded dies by doping aluminum used in bond pads during Cu/Low-k BEOL processing
LSI LOGIC CORP7 citations71
US6838379B1Jan 4, 2005
Process for reducing impurity levels, stress, and resistivity, and increasing grain size of copper filler in trenches and vias of integrated circuit structures to enhance electrical performance of copper filler
LSI LOGIC CORP9 citations71
US6555475B1Apr 29, 2003
Arrangement and method for polishing a surface of a semiconductor wafer
LSI LOGIC CORP6 citations70
US6489242B1Dec 3, 2002
Process for planarization of integrated circuit structure which inhibits cracking of low dielectric constant dielectric material adjacent underlying raised structures
LSI LOGIC CORP7 citations70
US6439981B1Aug 27, 2002
Arrangement and method for polishing a surface of a semiconductor wafer
LSI LOGIC CORP6 citations70
US6586326B2Jul 1, 2003
Metal planarization system
LSI LOGIC CORP3 citations62
US6372524B1Apr 16, 2002
Method for CMP endpoint detection
LSI LOGIC CORP4 citations62
US6951808B2Oct 4, 2005
Metal planarization system
LSI LOGIC CORP1 citations51
US6713394B2Mar 30, 2004
Process for planarization of integrated circuit structure which inhibits cracking of low dielectric constant dielectric material adjacent underlying raised structures
LSI LOGIC CORP1 citations48