Inventor

RINGE TUSHAR P

IN33 patents

⚠️ This page may combine multiple inventors who share the name “RINGE TUSHAR P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RINGE TUSHAR P

ADVANCED RISC MACH LTD

System, method and apparatus for enabling partial data transfers with indicators

Message protocol for a data processing system

High-performance streaming of ordered write stashes to enable optimized data sharing between I/O masters and CPUs

Configurable cache coherency controller

Apparatus and method for routing access requests in an interconnect

Data processing apparatus with snoop request address alignment and snoop response time alignment

Efficient support for variable width data channels in an interconnect network

Clock circuitry for functionally safe systems

System, method and apparatus for ordering logic

Cache for storing coherent and non-coherent data

Interconnect resource allocation

System, method and apparatus for accessing shared memory

Read transaction tracker lifetimes in a coherent interconnect system

Apparatus and method for processing burst read transactions

Separating completion and data responses for higher read throughput and lower link utilization in a data processing network

Snoop filter with imprecise encoding

Data processing network with flow compaction for streaming data transfer

I/O coherent request node for data processing network with improved handling of write operations

CCIX port management for PCI express traffic

Reset protection scheme for functional safety applications

Sending a request to agents coupled to an interconnect

Method and apparatus for efficient chip-to-chip data transfer

Transfer protocol in a data processing network

Apparatus and method for handling ordered transactions

Apparatus and method for handling memory access requests

Protocol layer tunneling for a data processing system

Clock circuitry with fault detection

Write operation status

Data processing network with super home node

Distributed virtual memory management for data processing network

Snooping with access permissions

Dynamic adaptation of direct memory transfer in a data processing system with mismatched data-bus widths

RINGE TUSHAR P

Context instruction cache architecture for a digital signal processor