P

Inventor

LAFONTANT GARY

US9 patents
⚠️ This page may combine multiple inventors who share the name “LAFONTANT GARY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

4 patents
US7271681B2Sep 18, 2007

Clearance hole size adjustment for impedance control in multilayer electronic packaging and printed circuit boards

IBM12 citations82
US9040418B2May 26, 2015

Enhanced capture pads for through semiconductor vias

IBM3 citations62
US8772949B2Jul 8, 2014

Enhanced capture pads for through semiconductor vias

IBM2 citations62
US8674506B2Mar 18, 2014

Structures and methods to reduce maximum current density in a solder ball

IBM1 citations51

FAROOQ MUKTA G

2 patents
US8288270B2Oct 16, 2012

Enhanced electromigration resistance in TSV structure and design

FAROOQ MUKTA G2 citations61
US8237288B1Aug 7, 2012

Enhanced electromigration resistance in TSV structure and design

FAROOQ MUKTA G3 citations61

DAUBENSPECK TIMOTHY H

1 patent
US8298929B2Oct 30, 2012

Offset solder vias, methods of manufacturing and design structures

DAUBENSPECK TIMOTHY H4 citations62

BEZAMA RASCHID J

1 patent
US8446006B2May 21, 2013

Structures and methods to reduce maximum current density in a solder ball

BEZAMA RASCHID J2 citations60

INTERRANTE MARIO J

1 patent
US8487447B2Jul 16, 2013

Semiconductor structure having offset passivation to reduce electromigration

INTERRANTE MARIO J2 citations56