Inventor
SEMKOW KRYSTYNA W
US41 patents
⚠️ This page may combine multiple inventors who share the name “SEMKOW KRYSTYNA W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
24 patentsUS5846598ADec 8, 1998
Electroless plating of metallic features on nonmetallic or semiconductor layer without extraneous plating
IBM269 citations99
US6060176AMay 9, 2000
Corrosion protection for metallic features
IBM96 citations98
US5098533AMar 24, 1992
Electrolytic method for the etch back of encapsulated copper-Invar-copper core structures
IBM66 citations95
US11244917B2Feb 8, 2022
Multilayer pillar for reduced stress interconnect and method of making same
IBM4 citations84
US10403590B2Sep 3, 2019
Multilayer pillar for reduced stress interconnect and method of making same
IBM4 citations84
US10396051B2Aug 27, 2019
Multilayer pillar for reduced stress interconnect and method of making same
IBM3 citations84
US9084378B2Jul 14, 2015
Under ball metallurgy (UBM) for improved electromigration
IBM11 citations84
US5108562AApr 28, 1992
Electrolytic method for forming vias and through holes in copper-invar-copper core structures
IBM21 citations79
US6203690B1Mar 20, 2001
Process of reworking pin grid array chip carriers
IBM12 citations73
US5560840AOct 1, 1996
Selective etching of nickle/iron alloys
IBM12 citations73
US5374338ADec 20, 1994
Selective electroetch of copper and other metals
IBM10 citations71
US7897059B2Mar 1, 2011
High tin solder etching solution
IBM4 citations63
US11171102B2Nov 9, 2021
Multilayer pillar for reduced stress interconnect and method of making same
IBM0 citations62
US11094657B2Aug 17, 2021
Multilayer pillar for reduced stress interconnect and method of making same
IBM0 citations62
US6838009B2Jan 4, 2005
Rework method for finishing metallurgy on chip carriers
IBM6 citations62
US6501174B2Dec 31, 2002
Interconnect structure for surface mounted devices
IBM5 citations61
US7294909B2Nov 13, 2007
Electronic package repair process
IBM2 citations60
US6823585B2Nov 30, 2004
Method of selective plating on a substrate
IBM2 citations60
US8025812B2Sep 27, 2011
Selective etch of TiW for capture pad formation
IBM5 citations54
US9640501B2May 2, 2017
Multilayer pillar for reduced stress interconnect and method of making same
IBM0 citations52
US8910853B2Dec 16, 2014
Additives for grain fragmentation in Pb-free Sn-based solder
IBM0 citations51
US8674506B2Mar 18, 2014
Structures and methods to reduce maximum current density in a solder ball
IBM1 citations51
US5472735ADec 5, 1995
Method for forming electrical connection to the inner layers of a multilayer circuit board
IBM1 citations50
US6916670B2Jul 12, 2005
Electronic package repair process
IBM1 citations49
ARVIN CHARLES L
9 patentsUS8177945B2May 15, 2012
Multi-anode system for uniform plating of alloys
ARVIN CHARLES L17 citations92
US8803317B2Aug 12, 2014
Structures for improving current carrying capability of interconnects and methods of fabricating the same
ARVIN CHARLES L5 citations84
US8232655B2Jul 31, 2012
Bump pad metallurgy employing an electrolytic Cu / electorlytic Ni / electrolytic Cu stack
ARVIN CHARLES L9 citations82
US8493746B2Jul 23, 2013
Additives for grain fragmentation in Pb-free Sn-based solder
ARVIN CHARLES L2 citations62
US9035459B2May 19, 2015
Structures for improving current carrying capability of interconnects and methods of fabricating the same
ARVIN CHARLES L1 citations52
US8623194B2Jan 7, 2014
Multi-anode system for uniform plating of alloys
ARVIN CHARLES L0 citations52
US8551303B2Oct 8, 2013
Multi-anode system for uniform plating of alloys
ARVIN CHARLES L0 citations52
US8587112B2Nov 19, 2013
Underbump metallurgy employing an electrolytic Cu / electorlytic Ni / electrolytic Cu stack
ARVIN CHARLES L0 citations51
US8268716B2Sep 18, 2012
Creation of lead-free solder joint with intermetallics
ARVIN CHARLES L0 citations48
JADHAV VIRENDRA R
3 patentsUS9472520B2Oct 18, 2016
Multilayer pillar for reduced stress interconnect and method of making same
JADHAV VIRENDRA R14 citations91
US8293587B2Oct 23, 2012
Multilayer pillar for reduced stress interconnect and method of making same
JADHAV VIRENDRA R9 citations91
US9111816B2Aug 18, 2015
Multilayer pillar for reduced stress interconnect and method of making same
JADHAV VIRENDRA R0 citations51