Inventor

PECHANEK GERALD GEORGE

US84 patents

⚠️ This page may combine multiple inventors who share the name “PECHANEK GERALD GEORGE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PECHANEK GERALD GEORGE

ALTERA CORP

Methods and apparatus for transforming, loading, and executing super-set instructions

Methods and apparatus for dynamic instruction controlled reconfigurable register file

Efficient complex multiplication and fast fourier transform (FFT) implementation on the ManArray architecture

Methods and apparatus for power control in a scalable array of processor elements

Methods and apparatus for address translation functions

Methods and apparatus for power control in a scalable array of processor elements

Methods and apparatus for adapting pipeline stage latency based on instruction type

Methods and apparatus for dynamic instruction controlled reconfigurable register file with extended precision

Efficient complex multiplication and fast fourier transform (FFT) implementation on the ManArray architecture

Methods and apparatus for efficient synchronous MIMD operations with IVLIW PE-TO-PE communication

Methods and apparatus for initiating and resynchronizing multi-cycle SIMD instructions

Manifold array processor

Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution

Methods and apparatus for single stage Galois field operations

Providing parallel operand functions using register file and extra path storage

Methods and apparatus for providing context switching between software tasks with reconfigurable control

Methods and apparatus for extracting bits of a source register based on a mask and right justifying the bits into a target register

Methods and apparatus for storing expanded width instructions in a VLIW memory for deferred execution

Methods and apparatus for scalable array processor interrupt detection and response

System core for transferring data between an external device and memory

Methods and apparatus for efficient complex long multiplication and covariance matrix implementation

Methods and apparatus for motion search refinement in a SIMD array processor

Methods and apparatus for dynamic instruction controlled reconfigurable register file

Methods and apparatus for scalable array processor interrupt detection and response

PECHANEK GERALD GEORGE

Interconnection network connecting operation-configurable nodes according to one or more levels of adjacency in multiple dimensions of communication in a multi-processor and a neural processor

Processor composed of memory nodes that execute memory access instructions and cooperate with execution nodes to execute function instructions

Methods and apparatus for creating and executing a packet of instructions organized according to data dependencies between adjacent instructions and utilizing networks based on adjacencies to transport data in response to execution of the instructions

Interconnection networks and methods of construction thereof for efficiently sharing memory and processing in a multiprocessor wherein connections are made according to adjacency of nodes in a dimension

Twisted and wrapped array organized into clusters of processing elements

Methods and apparatus for meta-architecture defined programmable instruction fetch functions supporting assembled variable length instruction processors

Methods and apparatus for signal flow graph pipelining that reduce storage of temporary variables

Communicaton across shared mutually exclusive direction paths between clustered processing elements

Methods and apparatus for independent processor node operations in a SIMD array processor

Meta-architecture defined programmable instruction fetch functions supporting assembled variable length instruction processors

Interconnection network and method of construction thereof for efficiently sharing memory and processing in a multi-processor wherein connections are made according to adjacency of nodes in a dimension

IBM

Massively parallel array processor

Massively parallel diagonal-fold tree array processor

Massively parallel multiple-folded clustered processor mesh array

Scalable parallel group partitioned diagonal-fold switching tree computing apparatus

Parallel diagonal-fold array processor

BARRY EDWIN FRANKLIN

Methods and apparatus for scalable array processor interrupt detection and response

Methods and apparatus for adapting pipeline stage latency based on instruction type

Methods and apparatus for scalable array processor interrupt detection and response

Methods and apparatus for adapting pipeline stage latency based on instruction type

PITSIANIS NIKOS P

Efficient complex multiplication and fast fourier transform (FFT) implementation on the ManArray architecture

Efficient complex multiplication and fast fourier transform (FFT) implementation on the ManArray architecture

STOJANCIC MIHAILO M

Methods and apparatus for providing a scalable deblocking filtering assist function within an array processor

Methods and apparatus for quarter-pel refinement in a SIMD array processor

PTS CORP

Methods and apparatus for automated generation of abbreviated instruction set and configurable processor architecture

VICORE TECHNOLOGIES INC

Methods and apparatus for independent processor node operations in a SIMD array processor