Inventor

ONTALUS VIOREL

US38 patents

⚠️ This page may combine multiple inventors who share the name “ONTALUS VIOREL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ONTALUS VIOREL

IBM

Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels

Bi-layer nFET embedded stressor element and integration to enhance drive current

Methods of fabricating optimization involving process sequence analysis

Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels

Field effect transistor and method of fabricating same

Method of reducing embedded SiGe loss in semiconductor device manufacturing

Data mining to detect performance quality of tools used repetitively in manufacturing

Source and drain doping profile control employing carbon-doped semiconductor material

Source and drain doping profile control employing carbon-doped semiconductor material

Gate structures and methods of manufacture

Semiconductor device including SOI butted junction to reduce short-channel penalty

Butted SOI junction isolation structures and devices and method of fabrication

Minimizing leakage current and junction capacitance in CMOS transistors by utilizing dielectric spacers

Semiconductor structure having test and transistor structures

GLOBALFOUNDRIES INC

Replacement body FinFET for improved junction profile with gate self-aligned junctions

Field-effect transistors with source/drain regions of reduced topography

Replacement body FinFET for improved junction profile with gate self-aligned junctions

Buffer layer for modulating Vt across devices

Semiconductor device including SIU butted junction to reduce short-channel penalty

Methods of modulating the morphology of epitaxial semiconductor material

GLOBALFOUNDRIES US INC

Heterojunction bipolar transistors with a cut stress liner

Semiconductor-on-insulator field effect transistor with performance-enhancing source/drain shapes and/or materials

Heterojunction bipolar transistor with marker layer

Bipolar junction transistor device with piezoelectric material positioned adjacent thereto

Transistor integration on a silicon-on-insulator substrate

Bipolar transistor

DUBE ABHISHEK

Cavity-free interface between extension regions and embedded silicon-carbon alloy source/drain regions

Reduced pattern loading for doped epitaxial process and semiconductor structure

DOMENICUCCI ANTHONY G

Method of fabricating a device using low temperature anneal processes, a device and design structure

Method of fabricating a device using low temperature anneal processes, a device and design structure

CHAN KEVIN K

Monolayer dopant embedded stressor for advanced CMOS

Monolayer dopant embedded stressor for advanced CMOS

JOHNSON JEFFREY B

Butted SOI junction isolation structures and devices and method of fabrication

ONTALUS VIOREL

Source and drain doping profile control employing carbon-doped semiconductor material

WEHELLA-GAMAGE DEEPAL

Reducing performance variation of narrow channel devices

CHIDAMBARRAO DURESETI

Minimizing leakage current and junction capacitance in CMOS transistors by utilizing dielectric spacers

KWON UNOH

Gate structures and methods of manufacture

DONEGAN JR DESMOND J

Forming CMOS with close proximity stressors