Inventor
DANSKIN JOHN M
US28 patents
⚠️ This page may combine multiple inventors who share the name “DANSKIN JOHN M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
NVIDIA CORP
17 patentsUS6894689B1May 17, 2005
Occlusion culling method and apparatus for graphics systems
NVIDIA CORP115 citations98
US6646639B1Nov 11, 2003
Modified method and apparatus for improved occlusion culling in graphics systems
NVIDIA CORP196 citations98
US6959110B1Oct 25, 2005
Multi-mode texture compression algorithm
NVIDIA CORP123 citations97
US7098922B1Aug 29, 2006
Multiple data buffers for processing graphics data
NVIDIA CORP58 citations96
US8040349B1Oct 18, 2011
System and method for structuring an A-buffer
NVIDIA CORP31 citations92
US7830392B1Nov 9, 2010
Connecting multiple pixel shaders to a frame buffer without a crossbar
NVIDIA CORP16 citations92
US7586492B2Sep 8, 2009
Real-time display post-processing using programmable hardware
NVIDIA CORP25 citations92
US8026912B1Sep 27, 2011
System and method for structuring an A-buffer
NVIDIA CORP12 citations84
US7979683B1Jul 12, 2011
Multiple simultaneous context architecture
NVIDIA CORP11 citations84
US7221368B1May 22, 2007
Stippled lines using direct distance evaluation
NVIDIA CORP14 citations84
US7342590B1Mar 11, 2008
Screen compression
NVIDIA CORP12 citations82
US7554546B1Jun 30, 2009
Stippled lines using direct distance evaluation
NVIDIA CORP7 citations74
US7622947B1Nov 24, 2009
Redundant circuit presents connections on specified I/O ports
NVIDIA CORP5 citations63
US6980208B1Dec 27, 2005
System and method for enhancing depth value processing in a graphics pipeline
NVIDIA CORP3 citations62
US8379033B2Feb 19, 2013
Method and system for improving data coherency in a parallel rendering system
NVIDIA CORP0 citations52
US7907145B1Mar 15, 2011
Multiple data buffers for processing graphics data
NVIDIA CORP0 citations52
US7965895B1Jun 21, 2011
Screen compression
NVIDIA CORP1 citations50
DANSKIN JOHN M
8 patentsUS8327071B1Dec 4, 2012
Interprocessor direct cache writes
DANSKIN JOHN M25 citations92
US8095782B1Jan 10, 2012
Multiple simultaneous context architecture for rebalancing contexts on multithreaded processing cores upon a context change
DANSKIN JOHN M38 citations92
US8775229B1Jul 8, 2014
Method of correcting a project schedule
DANSKIN JOHN M17 citations83
US8730249B2May 20, 2014
Parallel array architecture for a graphics processor
DANSKIN JOHN M6 citations83
US8654135B1Feb 18, 2014
A-Buffer compression for different compression formats
DANSKIN JOHN M10 citations83
US8553041B1Oct 8, 2013
System and method for structuring an A-buffer to support multi-sample anti-aliasing
DANSKIN JOHN M16 citations83
US8130223B1Mar 6, 2012
System and method for structuring an A-buffer to support multi-sample anti-aliasing
DANSKIN JOHN M18 citations83
US9092170B1Jul 28, 2015
Method and system for implementing fragment operation processing across a graphics bus interconnect
DANSKIN JOHN M0 citations40