Inventor

BAUMGARTNER JASON R

US72 patents

⚠️ This page may combine multiple inventors who share the name “BAUMGARTNER JASON R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BAUMGARTNER JASON R

IBM

Method and system for enhanced verification by closely coupling a structural overapproximation algorithm and a structural satisfiability solver

Method for predicate-based compositional minimization in a verification environment

Sequential equivalence checking for asynchronous verification

Method and system for performing utilization of traces for incremental refinement in coupling a structural overapproximation algorithm and a satisfiability solver

Method and system for performing minimization of input count during structural netlist overapproximation

Method and system for performing heuristic constraint simplification

Using constraints in design verification

Method and system for performing heuristic constraint simplification

Method and system for performing heuristic constraint simplification

Adaptive bug-search depth for simple and deep counterexamples

Initial-state and next-state value folding

Method, system and application for sequential cofactor-based analysis of netlists

Enhanced verification by closely coupling a structural satisfiability solver and rewriting algorithms

Method and system for sequential netlist reduction through trace-containment

Enhanced verification by closely coupling a structural overapproximation algorithm and a structural satisfiability solver

Method for heuristic preservation of critical inputs during sequential reparameterization

Enhanced verification by closely coupling a structural overapproximation algorithm and a structural satisfiability solver

Conjunctive BDD building and variable quantification using case-splitting

Method and system for performing target enlargement in the presence of constraints

Method and system for enhanced verification by closely coupling a structural satisfiability solver and rewriting algorithms

Method and system for performing target enlargement in the presence of constraints

Method and system for performing ternary verification

Adaptive bug-search depth for simple and deep counterexamples

Verification techniques for liveness checking of logic designs

Method and apparatus for performing equivalence checking on circuit designs having differing clocking and latching schemes

BAUMGARTNER JASON R

Techniques for performing conditional sequential equivalence checking of an integrated circuit logic design

Enhanced analysis of array-based netlists via reparameterization

Efficient Redundancy Identification, Redundancy Removal, and Sequential Equivalence Checking within Designs Including Memory Arrays.

Logic design verification techniques for liveness checking with retiming

Constructing inductive counterexamples in a multi-algorithm verification framework

Method and system for optimal diameter bounding of designs with complex feed-forward components

Efficiently determining boolean satisfiability with lazy constraints

Method and system for optimal counterexample-guided proof-based abstraction

Method and system for scalable reduction in registers with SAT-based resubstitution

Techniques for analysis of logic designs with transient logic

Minimizing memory array representations for enhanced synthesis and verification

Optimal correlated array abstraction

Scalable reduction in registers with SAT-based resubstitution

Method and system for design simplification through implication-based analysis

Predicate-based compositional minimization in a verification environment

Sequential encoding for relational analysis (SERA) of a software model

Enhanced analysis of array-based netlists via phase abstraction

Method and system for dynamic automated hint generation for enhanced reachability analysis

Efficiently determining Boolean satisfiability with lazy constraints

Enhancing redundancy removal with early merging

Tracking array data contents across three-valued read and write operations

Techniques for employing retiming and transient simplification on netlists that include memory arrays

Enhancing redundancy removal with early merging

ATASU KUBILAY

Verifying correctness of regular expression transformations that use a post-processor

CASE MICHAEL L

Logical circuit netlist reduction and model simplification using simulation results containing symbolic values