Inventor

CASE MICHAEL L

US25 patents

⚠️ This page may combine multiple inventors who share the name “CASE MICHAEL L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CASE MICHAEL L

BAUMGARTNER JASON R

Techniques for performing conditional sequential equivalence checking of an integrated circuit logic design

Enhanced analysis of array-based netlists via reparameterization

Efficient Redundancy Identification, Redundancy Removal, and Sequential Equivalence Checking within Designs Including Memory Arrays.

Constructing inductive counterexamples in a multi-algorithm verification framework

Method and system for optimal diameter bounding of designs with complex feed-forward components

Efficiently determining boolean satisfiability with lazy constraints

Method and system for optimal counterexample-guided proof-based abstraction

Method and system for scalable reduction in registers with SAT-based resubstitution

Techniques for analysis of logic designs with transient logic

Minimizing memory array representations for enhanced synthesis and verification

Optimal correlated array abstraction

Scalable reduction in registers with SAT-based resubstitution

Method and system for design simplification through implication-based analysis

Enhanced analysis of array-based netlists via phase abstraction

Efficiently determining Boolean satisfiability with lazy constraints

Enhancing redundancy removal with early merging

Tracking array data contents across three-valued read and write operations

Techniques for employing retiming and transient simplification on netlists that include memory arrays

Enhancing redundancy removal with early merging

Eliminating, coalescing, or bypassing ports in memory array representations

Array concatenation in an integrated circuit design

Method for scalable derivation of an implication-based reachable state set overapproximation

Automated convergence of ternary simulation by saturation of deep gates

CASE MICHAEL L

Logical circuit netlist reduction and model simplification using simulation results containing symbolic values

CALYPTO DESIGN SYSTEMS INC

Formal verification of booth multipliers