Inventor

KANZELMAN ROBERT L

US45 patents

⚠️ This page may combine multiple inventors who share the name “KANZELMAN ROBERT L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KANZELMAN ROBERT L

IBM

Method and system for enhanced verification by closely coupling a structural overapproximation algorithm and a structural satisfiability solver

Method for mapping in logic synthesis by logic classification

Method and system for performing utilization of traces for incremental refinement in coupling a structural overapproximation algorithm and a satisfiability solver

Method and system for performing minimization of input count during structural netlist overapproximation

Method and system for performing heuristic constraint simplification

Method and system for performing heuristic constraint simplification

Method and system for performing heuristic constraint simplification

Initial-state and next-state value folding

Method, system and application for sequential cofactor-based analysis of netlists

Enhanced verification by closely coupling a structural satisfiability solver and rewriting algorithms

Method and system for sequential netlist reduction through trace-containment

Enhanced verification by closely coupling a structural overapproximation algorithm and a structural satisfiability solver

Enhanced verification by closely coupling a structural overapproximation algorithm and a structural satisfiability solver

Method and system for performing target enlargement in the presence of constraints

Method and system for enhanced verification by closely coupling a structural satisfiability solver and rewriting algorithms

Method and system for performing target enlargement in the presence of constraints

Methods and apparatus for Boolean equivalency checking in the presence of voting logic

Equivalency verification for hierarchical references

Automated use of uninterpreted functions in sequential equivalence

Generating constraint preserving testcases in the presence of dead-end constraints

Method for scalable liveness verification via abstraction refinement

System and program product for scalable liveness verification via abstraction refinement

Trace equivalence identification through structural isomorphism detection with on the fly logic writing

Verification complexity reduction via range-preserving input-to-constant conversion

BAUMGARTNER JASON R

Enhanced analysis of array-based netlists via reparameterization

Efficient Redundancy Identification, Redundancy Removal, and Sequential Equivalence Checking within Designs Including Memory Arrays.

Constructing inductive counterexamples in a multi-algorithm verification framework

Method and system for optimal diameter bounding of designs with complex feed-forward components

Efficiently determining boolean satisfiability with lazy constraints

Method and system for optimal counterexample-guided proof-based abstraction

Techniques for analysis of logic designs with transient logic

Minimizing memory array representations for enhanced synthesis and verification

Optimal correlated array abstraction

Method and system for design simplification through implication-based analysis

Efficiently determining Boolean satisfiability with lazy constraints

Enhancing redundancy removal with early merging

Tracking array data contents across three-valued read and write operations

Techniques for employing retiming and transient simplification on netlists that include memory arrays

Enhancing redundancy removal with early merging

Eliminating, coalescing, or bypassing ports in memory array representations

Array concatenation in an integrated circuit design

Performing minimization of input count during structural netlist overapproximation

Trace containment detection of combinational designs via constraint-based uncorrelated equivalence checking

CASE MICHAEL L

Logical circuit netlist reduction and model simplification using simulation results containing symbolic values

ACUNA VICTOR A

Methods and apparatus for boolean equivalency checking in the presence of voting logic