Inventor

DAKSHINA-MURTHY SRIKANTESWARA

US79 patents

⚠️ This page may combine multiple inventors who share the name “DAKSHINA-MURTHY SRIKANTESWARA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DAKSHINA-MURTHY SRIKANTESWARA

ADVANCED MICRO DEVICES INC

Narrow fin FinFET

Strained channel FinFET

Epitaxially grown fin for FinFET

Semiconductor device having a U-shaped gate structure

Strained channel finfet

Modified film stack and patterning strategy for stress compensation and prevention of pattern distortion in amorphous carbon gate patterning

Method for forming fins in a FinFET device using sacrificial carbon layer

Control of bottom dimension of tapered contact via variation(s) of etch process

Use of amorphous carbon hard mask for gate patterning to eliminate requirement of poly re-oxidation

Finfet gate formation using reverse trim of dummy gate

Method for forming a fin in a finFET device

Narrow fin FinFET

Planar finFET patterning using amorphous carbon

Selective epitaxial growth for tunable channel thickness

FinFET gate formation using reverse trim and oxide polish

Method for fabricating a semiconductor device using amorphous carbon having improved etch resistance

Method for formation of a differential offset spacer

Method for alignment mark formation for a shallow trench isolation process

Method of using amorphous carbon film as a sacrificial layer in replacement gate integration processes

Post fabrication CD modification on imprint lithography mask

System and method for imprint lithography to facilitate dual damascene integration with two imprint acts

Epitaxially grown fin for FinFET

Using supercritical fluids to clean lenses and monitor defects

System and method for imprint lithography to facilitate dual damascene integration in a single imprint act

Self aligned damascene gate

Ion implantation to modulate amorphous carbon stress

Semiconductor device having a gate structure surrounding a fin

Formation of amorphous carbon ARC stack having graded transition between amorphous carbon and ARC material

Method for forming a gate in a FinFET device

Method for defect reduction and enhanced control over critical dimensions and profiles in semiconductor devices

Etch stop layer for etching FinFET gate over a large topography

Method of pinhole decoration and detection

Metal gate stack with etch stop layer

Metal gate stack with etch stop layer having implanted metal species

Real time immersion medium control using scatterometry

Use of multilayer amorphous carbon ARC stack to eliminate line warpage phenomenon

Method for forming alignment features and back-side contacts with fewer lithography and etch steps

Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication

Resist trim process to define small openings in dielectric layers

Method for photoresist trim endpoint detection

Method for forming integrated circuit

Feedback control of imprint mask feature profile using scatterometry and spacer etchback

Topography compensation of imprint lithography patterning

Optical monitoring and control of two layers of liquid immersion media

System and method using in situ scatterometry to detect photoresist pattern integrity during the photolithography process

Method of using amorphous carbon to prevent resist poisoning

Selective stress-inducing implant and resulting pattern distortion in amorphous carbon patterning

Method of reducing STI divot formation during semiconductor device fabrication

SPANSION LLC

Flash memory device

MOTOROLA INC

Capping layer for reducing amorphous carbon contamination of photoresist in semiconductor device manufacture; and process for making same