Inventor

HSU SHENG TENG

US361 patents

⚠️ This page may combine multiple inventors who share the name “HSU SHENG TENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HSU SHENG TENG

SHARP LAB OF AMERICA INC

CMOS active pixel sensor

Real-time CMOS imager having stacked photodiodes fabricated on SOI wafer

Strained silicon fin structure

Strained silicon finFET device

Buffered-layer memory cell

Trench isolated cross-point memory array

Shared bit line cross-point memory array incorporating P/N junctions

RRAM memory cell electrodes

Low cross-talk electrically programmable resistance cross point memory

Electrically programmable resistance cross point memory

CMOS self-aligned strapped interconnection

System and method of selectively cleaning copper substrate surfaces, in-situ, to remove copper oxides

Back-to-back metal/semiconductor/metal (MSM) Schottky diode

Metal/semiconductor/metal current limiter

Gallium nitride-on-silicon interface using multiple aluminum compound buffer layers

Metal/semiconductor/metal (MSM) back-to-back Schottky diode

Resistance random access memory devices and method of fabrication

Semiconductive metal oxide thin film ferroelectric memory transistor

Self-aligned cross point resistor memory array

Cross-point RRAM memory array having low bit line crosstalk

Cross-point resistor memory array

Memory resistance film with controlled oxygen content

PCMO thin film with resistance random access memory (RRAM) characteristics

3d rram

High-density SOI cross-point memory array and method for fabricating same

Method of fabricating trench isolated cross-point memory array

One mask PT/PCMO/PT stack etching process for RRAM applications

Device and method for reversible resistance change induced by electric pulses in non-crystalline perovskite unipolar programmable memory

Spin transistor magnetic random access memory device

Implantation at elevated temperatures for amorphization re-crystallization of Si1-xGex films on silicon substrates

Process integration of Si1-xGex CMOS with Si1-xGex relaxation after STI formation

Dual metal gate CMOS devices and method for making the same

Shared bit line cross point memory array

Molecular hydrogen implantation method for forming a relaxed silicon germanium layer with high germanium content

Single c-axis PGO thin film on ZrO2 for non-volatile memory applications and methods of making the same

Method of making low-K carbon doped silicon oxide

Dose control technique for plasma doping in ultra-shallow junction formations

Ferroelectric nonvolatile transistor and method of making same

Method of forming amorphous conducting diffusion barriers

Metal/ZnOx/metal current limiter

Method of fabricating nano-scale resistance cross-point memory array

Methods of fabricating a cross-point resistor memory array

System and method for isolating silicon germanium dislocation regions in strained-silicon CMOS applications

Temperature compensated RRAM circuit

Methods of manufacturing low cross-talk electrically programmable resistance cross point memory structures

1T1R resistive memory

Strained-silicon channel CMOS with sacrificial shallow trench isolation oxide liner

Methods of making relaxed silicon-germanium on insulator via layer transfer

SHARP MICROELECT TECH INC

Low resistance contact between integrated circuit metal levels and method for same

Method for manufacturing a CMOS self-aligned strapped interconnection