Inventor
HERRMANN TOM
DE21 patents
⚠️ This page may combine multiple inventors who share the name “HERRMANN TOM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
GLOBALFOUNDRIES INC
11 patentsUS9583640B1Feb 28, 2017
Method including a formation of a control gate of a nonvolatile memory cell and semiconductor structure
GLOBALFOUNDRIES INC30 citations93
US10121846B1Nov 6, 2018
Resistor structure with high resistance based on very thin semiconductor layer
GLOBALFOUNDRIES INC10 citations83
US8835255B2Sep 16, 2014
Method of forming a semiconductor structure including a vertical nanowire
GLOBALFOUNDRIES INC4 citations72
US10283584B2May 7, 2019
Capacitive structure in a semiconductor device having reduced capacitance variability
GLOBALFOUNDRIES INC1 citations60
US10580863B2Mar 3, 2020
Transistor element with reduced lateral electrical field
GLOBALFOUNDRIES INC1 citations56
US9711513B2Jul 18, 2017
Semiconductor structure including a nonvolatile memory cell and method for the formation thereof
GLOBALFOUNDRIES INC1 citations51
US8916928B2Dec 23, 2014
Threshold voltage adjustment in a fin transistor by corner implantation
GLOBALFOUNDRIES INC0 citations51
US10283642B1May 7, 2019
Thin body field effect transistor including a counter-doped channel area and a method of forming the same
GLOBALFOUNDRIES INC0 citations49
US10497803B2Dec 3, 2019
Fully depleted silicon on insulator (FDSOI) lateral double-diffused metal oxide semiconductor (LDMOS) for high frequency applications
GLOBALFOUNDRIES INC0 citations48
US10930777B2Feb 23, 2021
Laterally double diffused metal oxide semiconductor (LDMOS) device on fully depleted silicon on insulator (FDSOI) enabling high input voltage
GLOBALFOUNDRIES INC0 citations47
US10644152B1May 5, 2020
Buried-channel low noise transistors and methods of making such devices
GLOBALFOUNDRIES INC0 citations39
GLOBALFOUNDRIES US INC
4 patentsUS11837605B2Dec 5, 2023
Structure including transistor using buried insulator layer as gate dielectric and trench isolations in source and drain
GLOBALFOUNDRIES US INC0 citations61
US11929433B2Mar 12, 2024
Asymmetric FET for FDSOI devices
GLOBALFOUNDRIES US INC0 citations56
US11245032B2Feb 8, 2022
Asymmetric FET for FDSOI devices
GLOBALFOUNDRIES US INC0 citations56
US12532501B2Jan 20, 2026
Structure with back-gate having oppositely doped semiconductor regions
GLOBALFOUNDRIES US INC0 citations54
BALDAUF TIM
3 patentsUS8912606B2Dec 16, 2014
Integrated circuits having protruding source and drain regions and methods for forming integrated circuits
BALDAUF TIM16 citations81
US8580643B2Nov 12, 2013
Threshold voltage adjustment in a Fin transistor by corner implantation
BALDAUF TIM4 citations60
US8941187B2Jan 27, 2015
Strain engineering in three-dimensional transistors based on strained isolation material
BALDAUF TIM0 citations39