Inventor

PRAMANIK DIPANKAR

US127 patents

⚠️ This page may combine multiple inventors who share the name “PRAMANIK DIPANKAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PRAMANIK DIPANKAR

VLSI TECHNOLOGY INC

Anti-fuse structure for reducing contamination of the anti-fuse material

Method of making high resistive structures in salicided process semiconductor devices

Method for leak detection in etching chambers

Method and structure for suppressing stress-induced defects in integrated circuit conductive lines

Method improving integrated circuit planarization during etchback

Methods of forming a semiconductor device

Method and apparatus for detecting edges under an opaque layer

Method for reducing contamination of anti-fuse material in an anti-fuse structure

Charge neutralization using silicon-enriched oxide layer

Charge neutralization using silicon-enriched oxide layer

Silicon corner rounding in shallow trench isolation process

Method for suppressing charge loss in EEPROMs/EPROMS and instabilities in SRAM load resistors

Anti-fuse structure for reducing contamination of the anti-fuse material

Device reliability of MOS devices using silicon rich plasma oxide films

Method for forming reliable MOS devices using silicon rich plasma oxide film

Method improving integrated circuit planarization during etchback

INTERMOLECULAR INC

Methods of manufacturing embedded bipolar switching resistive memory

Tunneling barrier creation in MSM stack as a selector device for non-volatile memory application

Switching conditions for resistive random access memory cells

Amorphous silicon doped with fluorine for selectors of resistive random access memory cells

Resistive random access memory cells having metal alloy current limiting layers

Method for improving data retention of ReRAM chips operating at low operating temperatures

Controlling ReRam forming voltage with doping

Nonvolatile resistive memory element with an oxygen-gettering layer

Controlling ReRam forming voltage with doping

Resistive random access memory cells having metal alloy current limiting layers

Multifunctional electrode

SYNOPSYS INC

Filler cells for design optimization in a place-and-route system

Selectively applying resolution enhancement techniques to improve performance and manufacturing cost of integrated circuits

Managing integrated circuit stress using dummy diffusion regions

Mask cost driven logic optimization and synthesis

Managing integrated circuit stress using dummy diffusion regions

Stress-managed revision of integrated circuit layouts

Method of correlating silicon stress to device instance parameters for circuit simulation

Managing integrated circuit stress using stress adjustment trenches

Analysis of stress impact on transistor performance

MOROZ VICTOR

Analysis of stress impact on transistor performance

Stress-managed revision of integrated circuit layouts

Analysis of stress impact on transistor performance

Analysis of stress impact on transistor performance

PRAMANIK DIPANKAR

Method for forming metal oxides and silicides in a memory device

Creating an embedded reram memory from a high-K metal gate transistor structure

System and method for modifying a data set of a photomask

WANG YUN

Atomic layer deposition of metal oxide materials for memory applications

Atomic layer deposition of metal oxide materials for memory applications

LIN XI-WEI

Method of correlating silicon stress to device instance parameters for circuit simulation

Filler cells for design optimization in a place-and-route system

KONINKL PHILIPS ELECTRONICS NV

Integrated circuit with relative sense inversion of signals along adjacent parallel signal paths

(unassigned)

Method enhancing planarization etchback margin, reliability, and stability of a semiconductor device

CADENCE DESIGN SYSTEMS INC

System and method for modifying a data set of a photomask