Inventor

CAPPELLANI ANNALISA

US51 patents

⚠️ This page may combine multiple inventors who share the name “CAPPELLANI ANNALISA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CAPPELLANI ANNALISA

INTEL CORP

Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate

Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode

Method for making semiconductor device having a high-k gate dielectric layer and a metal gate electrode

Conversion of strain-inducing buffer to electrical insulator

CMOS nanowire structure

Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition

Silicon and silicon germanium nanowire structures

Method for making a semiconductor device having a high-k dielectric layer and a metal gate electrode

Gate contact structure over active gate and method to fabricate same

Semiconductor device with isolated body portion

Gate-all-around (GAA) transistors with nanowires on an isolation pedestal

Gate-all-around (GAA) transistor with stacked nanowires on locally isolated substrate

Uniaxially strained nanowire structure

Conversion of strain-inducing buffer to electrical insulator

Gate contact structure over active gate and method to fabricate same

Uniaxially strained nanowire structure

Gate contact structure over active gate and method to fabricate same

Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates

Semiconductor device having metallic source and drain regions

Silicon and silicon germanium nanowire structures

Nanowire structures having non-discrete source and drain regions

Isolated and bulk semiconductor devices formed on a same bulk substrate

CAPPELLANI ANNALISA

Multi-gate semiconductor device with self-aligned epitaxial source and drain

Semiconductor device with isolated body portion

Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates

Methods for fabricating strained gate-all-around semiconductor devices by fin oxidation using an undercut etch-stop layer

Conversion of strain-inducing buffer to electrical insulator

Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates

Semiconductor devices having modulated nanowire counts

Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition

Isolated and bulk semiconductor devices formed on a same bulk substrate

Semiconductor devices having three-dimensional bodies with modulated heights

Junctionless accumulation-mode devices on prominent architectures, and methods of making same

CEA STEPHEN M

Uniaxially strained nanowire structure

Nanowire structures having non-discrete source and drain regions

Nanowire structures having non-discrete source and drain regions

INFINEON TECHNOLOGIES AG

Method for fabricating a MOSFET having a very small channel length

Semiconductor component, method for producing the semiconductor component, and method for producing electrical connections between individual circuit elements

Method for roughening a surface of a semiconductor substrate

KUHN KELIN J

Silicon and silicon germanium nanowire structures

Silicon and silicon germanium nanowire structures

KIM SEIYON

CMOS nanowire structure

CMOS nanowire structure

GOOGLE LLC

Nanowire structures having non-discrete source and drain regions

Nanowire structures having non-discrete source and drain regions

PETHE ABHIJIT JAYANT

Gate contact structure over active gate and method to fabricate same

KAVALIEROS JACK

Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate

GILES MARTIN D

Semiconductor device having metallic source and drain regions

SONY GROUP CORP

Silicon and silicon germanium nanowire structures

SONY CORP

Silicon and silicon germanium nanowire structures