Inventor

KUHN KELIN J

US79 patents

⚠️ This page may combine multiple inventors who share the name “KUHN KELIN J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KUHN KELIN J

INTEL CORP

Thin tensile layers in shallow trench isolation and method of making same

Nanowire transistor devices and forming techniques

Integration methods to fabricate internal spacers for nanowire devices

Conversion of strain-inducing buffer to electrical insulator

CMOS fabrication process utilizing special transistor orientation

Thin tensile layers in shallow trench isolation and method of making same

CMOS nanowire structure

Nanowire transistor devices and forming techniques

Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition

Silicon and silicon germanium nanowire structures

Semiconductor device with isolated body portion

Integration methods to fabricate internal spacers for nanowire devices

Internal spacers for nanowire transistors and method of fabrication thereof

Power switches having positive-channel high dielectric constant insulated gate field effect transistors

Method of fabricating CMOS FinFETs by selectively etching a strained SiGe layer

Method of fabricating a semiconductor device with strained SiGe fins and a Si cladding layer

Integration methods to fabricate internal spacers for nanowire devices

CMOS FinFET device with dual strained cladding layers on relaxed SiGe fins, and method of fabricating the same

Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs

Conversion of strain-inducing buffer to electrical insulator

Quantum key distribution (QSD) scheme using photonic integrated circuit (PIC)

Power switches having positive-channel high dielectric constant insulated gate field effect transistors

Non-planar semiconductor device having hybrid geometry-based active region

Non-planar semiconductor device having hybrid geometry-based active region

Internal spacers for nanowire transistors and method of fabrication thereof

CAPPELLANI ANNALISA

Semiconductor device with isolated body portion

Conversion of strain-inducing buffer to electrical insulator

Semiconductor devices having modulated nanowire counts

Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition

Isolated and bulk semiconductor devices formed on a same bulk substrate

Semiconductor devices having three-dimensional bodies with modulated heights

KUHN KELIN J

Silicon and silicon germanium nanowire structures

Silicon and silicon germanium nanowire structures

Copper-filled trench contact for transistor performance improvement

Copper-filled trench contact for transistor performance improvement

KIM SEIYON

Integration methods to fabricate internal spacers for nanowire devices

CMOS nanowire structure

CMOS nanowire structure

CEA STEPHEN M

Non-planar device having uniaxially strained semiconductor body and method of making same

Nanowire structures having non-discrete source and drain regions

Nanowire structures having non-discrete source and drain regions

SONY GROUP CORP

Nanowire transistor fabrication with hardmask layers

Integration methods to fabricate internal spacers for nanowire devices

Silicon and silicon germanium nanowire structures

GLASS GLENN A

Nanowire transistor devices and forming techniques

TRUSTEES LELAND STANFORD UNIVE

Method and apparatus for cooling a slab laser

KOTLYAR ROZA

Tunneling field effect transistors (TFETs) for CMOS approaches to fabricating N-type and P-type TFETs

UNIV LELAND STANFORD JUNIOR

Method and apparatus for pumping lasant slabs

MANIPATRUNI SASIKANTH

Method and apparatus for managing and accessing personal data

GOOGLE LLC

Non-planar semiconductor device having hybrid geometry-based active region