Inventor

CEA STEPHEN M

US108 patents

⚠️ This page may combine multiple inventors who share the name “CEA STEPHEN M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CEA STEPHEN M

INTEL CORP

Bulk non-planar transistor having strained enhanced mobility and methods of fabrication

Bulk non-planar transistor having strained enhanced mobility and methods of fabrication

Gate-induced strain for MOS performance improvement

Conversion of strain-inducing buffer to electrical insulator

Isolated tri-gate transistor fabricated on bulk substrate

Bulk non-planar transistor having strained enhanced mobility and methods of fabrication

Transistor with strain-inducing structure in channel

Method of forming a shallow junction

Flash lamp annealing apparatus to generate electromagnetic radiation having selective wavelengths

Stacked channel structures for MOSFETs

Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices

High mobility strained channels for fin-based NMOS transistors

CMOS nanowire structure

Silicon and silicon germanium nanowire structures

Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation

High mobility strained channels for fin-based transistors

Semiconductor device with isolated body portion

Forksheet transistors with dielectric or conductive spine

Gate-induced strain for MOS performance improvement

Method of fabricating CMOS FinFETs by selectively etching a strained SiGe layer

Buried etch-stop layer to help control transistor source/drain depth

Device isolation

Method of fabricating a semiconductor device with strained SiGe fins and a Si cladding layer

Backside fin recess control with multi-hsi option

Semiconductor nanowire device having cavity spacer and method of fabricating cavity spacer for semiconductor nanowire device

Hybrid trigate and nanowire CMOS device architecture

CMOS FinFET device with dual strained cladding layers on relaxed SiGe fins, and method of fabricating the same

Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs

Uniaxially strained nanowire structure

High mobility strained channels for fin-based transistors

Two-dimensional condensation for uniaxially strained semiconductor fins

Conversion of strain-inducing buffer to electrical insulator

CEA STEPHEN M

High mobility strained channels for fin-based transistors

Uniaxially strained nanowire structure

Non-planar device having uniaxially strained semiconductor body and method of making same

Methods and apparatus to reduce layout based strain variations in non-planar transistor structures

Nanowire structures having non-discrete source and drain regions

Nanowire structures having non-discrete source and drain regions

Methods and apparatus to reduce layout based strain variations in non-planar transistor structures

KUHN KELIN J

Silicon and silicon germanium nanowire structures

Silicon and silicon germanium nanowire structures

KIM SEIYON

CMOS nanowire structure

CMOS nanowire structure

CAPPELLANI ANNALISA

Semiconductor device with isolated body portion

Conversion of strain-inducing buffer to electrical insulator

KAVALIEROS JACK T

Two-dimensional condensation for uniaxially strained semiconductor fins

RAKSHIT TITASH

Trigate transistor having extended metal gate electrode

KOTLYAR ROZA

Tunneling field effect transistors (TFETs) for CMOS approaches to fabricating N-type and P-type TFETs

GLASS GLENN A

Conversion of thin transistor elements from silicon to silicon germanium

BOHR MARK T

Through gate fin isolation