Inventor

ZHANG XUNYUAN

US124 patents

⚠️ This page may combine multiple inventors who share the name “ZHANG XUNYUAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ZHANG XUNYUAN

GLOBALFOUNDRIES INC

Method and apparatus for placing a gate contact inside a semiconductor active region having high-k dielectric gate caps

Methods of forming V0 structures for semiconductor devices that includes recessing a contact structure

Integrated circuits and methods for fabricating integrated circuits with reduced parasitic capacitance

Topological method to build self-aligned MTJ without a mask

Metal interconnects for super (skip) via integration

Skip via structures

Methods for fabricating integrated circuits including barrier layers for interconnect structures

Hybrid manganese and manganese nitride barriers for back-end-of-line metallization and methods for fabricating the same

Middle of the line (MOL) metal contacts

Self-aligned metal wire on contact structure and method for forming same

Self aligned interconnect structures

Method to form air-gap spacers and air-gap spacer-containing structures

Methods of forming integrated circuit structure using extreme ultraviolet photolithography technique and related integrated circuit structure

Inverted damascene interconnect structures

Pre-spacer self-aligned cut formation

Method and apparatus for placing a gate contact inside an active region of a semiconductor

Self aligned interconnect structures

Method of forming a gate contact structure for a semiconductor device

Devices and methods of forming low resistivity noble metal interconnect

Methods that use at least a dual damascene process and, optionally, a single damascene process to form interconnects with hybrid metallization and the resulting structures

Methods of forming ruthenium conductive structures in a metallization layer

Methods for fabricating integrated circuits including back-end-of-the-line interconnect structures

Methods, apparatus and system for forming a dielectric field for dual orientation self aligned vias

Semiconductor device with low-K spacers

Method and device for self-aligned contact on a non-recessed metal gate

Methods for fabricating integrated circuits with improved contact structures

Selective growth of a work-function metal in a replacement metal gate of a semiconductor device

Semiconductor device having a self-forming barrier layer at via bottom

Multi-layer barrier layer stacks for interconnect structures

Subtractive metal multi-layer barrier layer for interconnect structure

Metal-insulator-metal capacitors with dielectric inner spacers

Cobalt interconnects formed by selective bottom-up fill

Sidewall spacer pattern formation method

Methods of self-forming barrier integration with pore stuffed ULK material

Methods of forming conductive copper-based structures using a copper-based nitride seed layer without a barrier layer and the resulting device

Methods for fabricating integrated circuits using chemical mechanical planarization to recess metal

Etch profile control during skip via formation

Methods of forming V0 structures for semiconductor devices by forming a protection layer with a non-uniform thickness

Fully aligned via in ground rule region

Method and apparatus for placing a gate contact inside a semiconductor active region having high-k dielectric gate caps

Method of making self-aligned continuity cuts in mandrel and non-mandrel metal lines

Method of making self-aligned continuity cuts in mandrel and non-mandrel metal lines

Raised fin structures and methods of fabrication

Interconnect structures

TANWAR KUNALJEET

Methods for fabricating integrated circuits with ruthenium-lined copper

GLOBALFOUNDARIES INC

Methods of forming a semiconductor device with low-k spacers and the resulting device

GLOBAL FOUNDRIES INC

Methods of selectively forming ruthenium liner layer

CAI XIUYU

Methods for forming an integrated circuit with straightened recess profile

ZHANG XUNYUAN

Semiconductor devices with copper interconnects and methods for fabricating same

LIN SEAN X

Methods of forming copper-based conductive structures on an integrated circuit device